Index: gcc/ChangeLog.aarch64
===================================================================
--- gcc/ChangeLog.aarch64	(revision 192534)
+++ gcc/ChangeLog.aarch64	(working copy)
@@ -1,3 +1,9 @@
+2012-10-17  Sofiane Naci  <sofiane.naci@arm.com>
+
+	* config/aarch64/aarch64.md (<optab><mode>3): Update constraint
+	for operand 0.
+	Update scheduling attribute for the second alternative.
+
 2012-10-16  Tejas Belagod  <tejas.belagod@arm.com>
 
 	* config/aarch64/arm_neon.h (vmla_lane_f32, vmla_lane_s16,
Index: gcc/config/aarch64/aarch64.md
===================================================================
--- gcc/config/aarch64/aarch64.md	(revision 192534)
+++ gcc/config/aarch64/aarch64.md	(working copy)
@@ -1995,12 +1995,12 @@
 ;; -------------------------------------------------------------------
 
 (define_insn "<optab><mode>3"
-  [(set (match_operand:GPI 0 "register_operand" "=r,r")
+  [(set (match_operand:GPI 0 "register_operand" "=r,rk")
 	(LOGICAL:GPI (match_operand:GPI 1 "register_operand" "%r,r")
 		     (match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>")))]
   ""
   "<logical>\\t%<w>0, %<w>1, %<w>2"
-  [(set_attr "v8type" "logic")
+  [(set_attr "v8type" "logic,logic_imm")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*<LOGICAL:optab>_<SHIFT:optab><mode>3"