> Subject: [PATCH][AArch64] Restrict usage of SBFIZ to valid range only
>
> This fixes an issue where we were generating an SBFIZ with
> operand 3 outside of the valid range (as determined by the
> size of the destination register and the amount of shift).
>
> My patch checks that the range is valid before allowing
> the pattern to be used.
>
> This has now had full regression testing and all is OK.
>
> OK for aarch64-trunk and aarch64-4_7-branch?
>
> Cheers,
> Ian
>
>
> 2012-10-15 Ian Bolton <ian.bol...@arm.com>
>
> * gcc/config/aarch64/aarch64.md
> (<optab><ALLX:mode>_shft_<GPI:mode>): Restrict based on op2.
>
>
> -------------------------
>
>
> diff --git a/gcc/config/aarch64/aarch64.md
> b/gcc/config/aarch64/aarch64.md
> index e6086a9..3bfe6e6 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -2311,7 +2311,7 @@
> (ashift:GPI (ANY_EXTEND:GPI
> (match_operand:ALLX 1 "register_operand" "r"))
> (match_operand 2 "const_int_operand" "n")))]
> - ""
> + "<ALLX:sizen> <= (<GPI:sizen> - UINTVAL (operands[2]))"
> "<su>bfiz\\t%<GPI:w>0, %<GPI:w>1, %2, #<ALLX:sizen>"
> [(set_attr "v8type" "bfm")
> (set_attr "mode" "<GPI:MODE>")]
>
>
>
New and improved version is at the end of this email.
This has had full regression testing and all is OK.
OK for aarch64-trunk and aarch64-4_7-branch?
Cheers,
Ian
2012-10-16 Ian Bolton <ian.bol...@arm.com>
* gcc/config/aarch64/aarch64.md
(<optab><ALLX:mode>_shft_<GPI:mode>): Restrict operands.
------------------------------------
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index e6086a9..e77496f 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2311,8 +2311,13 @@
(ashift:GPI (ANY_EXTEND:GPI
(match_operand:ALLX 1 "register_operand" "r"))
(match_operand 2 "const_int_operand" "n")))]
- ""
- "<su>bfiz\\t%<GPI:w>0, %<GPI:w>1, %2, #<ALLX:sizen>"
+ "UINTVAL (operands[2]) < <GPI:sizen>"
+{
+ operands[3] = (<ALLX:sizen> <= (<GPI:sizen> - UINTVAL (operands[2])))
+ ? GEN_INT (<ALLX:sizen>)
+ : GEN_INT (<GPI:sizen> - UINTVAL (operands[2]));
+ return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
+}
[(set_attr "v8type" "bfm")
(set_attr "mode" "<GPI:MODE>")]
)
