Hello,
this patch provides an alternate pattern to let combine recognize scalar
operations that preserve the high part of a vector. If the strategy is all
right, I could do the same for more operations (mul, div, ...). Something
similar is also possible for V4SF (different pattern though), but probably
not as useful.
bootstrap+testsuite ok.
2012-10-13 Marc Glisse <marc.gli...@inria.fr>
PR target/54855
gcc/
* config/i386/sse.md (*sse2_vm<plusminus_insn>v2df3): New define_insn.
gcc/testsuite/
* gcc.target/i386/pr54855.c: New testcase.
--
Marc GlisseIndex: config/i386/sse.md
===================================================================
--- config/i386/sse.md (revision 192420)
+++ config/i386/sse.md (working copy)
@@ -812,20 +812,38 @@
(const_int 1)))]
"TARGET_SSE"
"@
<plusminus_mnemonic><ssescalarmodesuffix>\t{%2, %0|%0, %2}
v<plusminus_mnemonic><ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseadd")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<ssescalarmode>")])
+(define_insn "*sse2_vm<plusminus_insn>v2df3"
+ [(set (match_operand:V2DF 0 "register_operand" "=x,x")
+ (vec_concat:V2DF
+ (plusminus:DF
+ (vec_select:DF
+ (match_operand:V2DF 1 "register_operand" "0,x")
+ (parallel [(const_int 0)]))
+ (match_operand:DF 2 "nonimmediate_operand" "xm,xm"))
+ (vec_select:DF (match_dup 1) (parallel [(const_int 1)]))))]
+ "TARGET_SSE2"
+ "@
+ <plusminus_mnemonic>sd\t{%2, %0|%0, %2}
+ v<plusminus_mnemonic>sd\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseadd")
+ (set_attr "prefix" "orig,vex")
+ (set_attr "mode" "DF")])
+
(define_expand "mul<mode>3"
[(set (match_operand:VF 0 "register_operand")
(mult:VF
(match_operand:VF 1 "nonimmediate_operand")
(match_operand:VF 2 "nonimmediate_operand")))]
"TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
(define_insn "*mul<mode>3"
[(set (match_operand:VF 0 "register_operand" "=x,x")
Index: testsuite/gcc.target/i386/pr54855.c
===================================================================
--- testsuite/gcc.target/i386/pr54855.c (revision 0)
+++ testsuite/gcc.target/i386/pr54855.c (revision 0)
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O -msse2" } */
+
+typedef double vec __attribute__((vector_size(16)));
+
+vec f (vec x)
+{
+ x[0] += 2;
+ return x;
+}
+
+vec g (vec x)
+{
+ x[0] -= 1;
+ return x;
+}
+
+/* { dg-final { scan-assembler-not "mov" } } */
Property changes on: testsuite/gcc.target/i386/pr54855.c
___________________________________________________________________
Added: svn:keywords
+ Author Date Id Revision URL
Added: svn:eol-style
+ native
