Make both cores selectable with -mcpu= and -mtune=, and give each one
its own cost model.
The costs are taken from the scheduling models LLVM carries for these
cores, SiFiveP500Model for the P550 and SiFiveP800Model for the
P870-D: three micro-ops issued per cycle against six, and the integer
and floating-point latencies of the respective pipelines.
The P870-D handles unaligned scalar and vector accesses, which the
P550 does not, so only the former sets overlap_op_by_pieces. The P550
has no vector unit and so no vector cost table of its own.
Neither core gets a pipeline description yet; both point at the
sifive_p600 one for now.
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Add sifive-p550 and
sifive-p870-d.
(RISCV_CORE): Add sifive-p550 and sifive-p870-d.
* config/riscv/riscv.cc (sifive_p550_tune_info): New.
(sifive_p870_tune_info): New.
* doc/riscv-mcpu.texi: Regenerate.
* doc/riscv-mtune.texi: Regenerate.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-sifive-p550.c: New test.
* gcc.target/riscv/mcpu-sifive-p870-d.c: New test.
---
gcc/config/riscv/riscv-cores.def | 10 ++++
gcc/config/riscv/riscv.cc | 50 +++++++++++++++++++
gcc/doc/riscv-mcpu.texi | 4 ++
gcc/doc/riscv-mtune.texi | 4 ++
.../gcc.target/riscv/mcpu-sifive-p550.c | 19 +++++++
.../gcc.target/riscv/mcpu-sifive-p870-d.c | 47 +++++++++++++++++
6 files changed, 134 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-sifive-p550.c
create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-sifive-p870-d.c
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index e7ae1cb934f..f9622d2453d 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -40,6 +40,8 @@ RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info)
RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
+RISCV_TUNE("sifive-p550", sifive_p600, sifive_p550_tune_info)
+RISCV_TUNE("sifive-p870-d", sifive_p600, sifive_p870_tune_info)
RISCV_TUNE("tt-ascalon-x", tt_ascalon_d8, tt_ascalon_d8_tune_info)
RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
RISCV_TUNE("xt-c908", xt_c908, xt_c908_tune_info)
@@ -112,11 +114,19 @@ RISCV_CORE("sifive-p450",
"rv64imafdc_za64rs_zic64b_zicbom_zicbop_zicboz_"
"ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_"
"zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs",
"sifive-p400-series")
+RISCV_CORE("sifive-p550", "rv64imafdc_zifencei_zfhmin_zba_zbb",
+ "sifive-p550")
RISCV_CORE("sifive-p670", "rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_"
"ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_"
"zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs_"
"zvl128b_zvbb_zvknc_zvkng_zvksc_zvksg",
"sifive-p600-series")
+RISCV_CORE("sifive-p870-d", "rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_"
+ "ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_"
+ "zifencei_zihintntl_zihintpause_zihpm_zimop_"
+ "za64rs_zama16b_zawrs_zfa_zfh_zcb_zcmop_zkr_zkt_"
+ "zvbb_zvfbfwma_zvfh_zvfhmin_zvknc_zvksg",
+ "sifive-p870-d")
RISCV_CORE("thead-c906",
"rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
"xtheadcondmov_xtheadfmemidx_xtheadmac_"
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f79b55a0c70..27b15aeacb3 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -595,6 +595,56 @@ static const struct riscv_tune_param sifive_p600_tune_info
= {
true, /* prefer-agnostic. */
};
+/* Costs to use when optimizing for SiFive P550. */
+static const struct riscv_tune_param sifive_p550_tune_info = {
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_add */
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_mul */
+ {COSTS_N_INSNS (19), COSTS_N_INSNS (33)}, /* fp_div */
+ {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* int_mul */
+ {COSTS_N_INSNS (20), COSTS_N_INSNS (35)}, /* int_div */
+ 3, /* issue_rate */
+ 4, /* branch_cost */
+ 3, /* memory_cost */
+ 4, /* fmv_cost */
+ true, /*
slow_unaligned_access */
+ false, /* vector_unaligned_access */
+ false, /* use_divmod_expansion */
+ false, /* overlap_op_by_pieces */
+ true, /* use_zero_stride_load
*/
+ false, /* speculative_sched_vsetvl */
+ RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI, /* fusible_ops */
+ NULL, /* vector cost */
+ NULL, /* function_align */
+ NULL, /* jump_align */
+ NULL, /* loop_align */
+ false, /* prefer-agnostic. */
+};
+
+/* Costs to use when optimizing for SiFive P870-D. */
+static const struct riscv_tune_param sifive_p870_tune_info = {
+ {COSTS_N_INSNS (2), COSTS_N_INSNS (2)}, /* fp_add */
+ {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* fp_mul */
+ {COSTS_N_INSNS (6), COSTS_N_INSNS (11)}, /* fp_div */
+ {COSTS_N_INSNS (2), COSTS_N_INSNS (2)}, /* int_mul */
+ {COSTS_N_INSNS (20), COSTS_N_INSNS (35)}, /* int_div */
+ 6, /* issue_rate */
+ 4, /* branch_cost */
+ 3, /* memory_cost */
+ 4, /* fmv_cost */
+ false, /* slow_unaligned_access */
+ true, /*
vector_unaligned_access */
+ false, /* use_divmod_expansion */
+ true, /* overlap_op_by_pieces
*/
+ true, /* use_zero_stride_load
*/
+ false, /* speculative_sched_vsetvl */
+ RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI, /* fusible_ops */
+ &generic_vector_cost, /* vector cost */
+ NULL, /* function_align */
+ NULL, /* jump_align */
+ NULL, /* loop_align */
+ true, /* prefer-agnostic. */
+};
+
/* Costs to use when optimizing for T-HEAD c906. */
static const struct riscv_tune_param thead_c906_tune_info = {
{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
diff --git a/gcc/doc/riscv-mcpu.texi b/gcc/doc/riscv-mcpu.texi
index 6e3c2adc2fb..f8ed60a3189 100644
--- a/gcc/doc/riscv-mcpu.texi
+++ b/gcc/doc/riscv-mcpu.texi
@@ -44,8 +44,12 @@ by particular CPU name. Permissible values for this option
are:
@samp{sifive-p450},
+@samp{sifive-p550},
+
@samp{sifive-p670},
+@samp{sifive-p870-d},
+
@samp{thead-c906},
@samp{xt-c908},
diff --git a/gcc/doc/riscv-mtune.texi b/gcc/doc/riscv-mtune.texi
index 101d81d3709..254c679e07d 100644
--- a/gcc/doc/riscv-mtune.texi
+++ b/gcc/doc/riscv-mtune.texi
@@ -30,6 +30,10 @@ particular CPU name. Permissible values for this option are:
@samp{sifive-p600-series},
+@samp{sifive-p550},
+
+@samp{sifive-p870-d},
+
@samp{tt-ascalon-x},
@samp{thead-c906},
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p550.c
b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p550.c
new file mode 100644
index 00000000000..5740c7d6087
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p550.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=unset -mcpu=sifive-p550 -mabi=lp64d" } */
+/* SiFive p550 => rv64imafdc_zifencei_zfhmin_zba_zbb */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_c) \
+ && defined(__riscv_zifencei) \
+ && defined(__riscv_zfhmin) \
+ && defined(__riscv_zba) \
+ && defined(__riscv_zbb))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p870-d.c
b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p870-d.c
new file mode 100644
index 00000000000..b8047bccdd2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p870-d.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=unset -mcpu=sifive-p870-d -mabi=lp64d" } */
+/* SiFive p870-d =>
rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zama16b_zawrs_zfa_zfh_zcb_zcmop_zkr_zkt_zvbb_zvfbfwma_zvfh_zvfhmin_zvknc_zvksg
*/
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_c) \
+ && defined(__riscv_b) \
+ && defined(__riscv_v) \
+ && defined(__riscv_zic64b) \
+ && defined(__riscv_zicbom) \
+ && defined(__riscv_zicbop) \
+ && defined(__riscv_zicboz) \
+ && defined(__riscv_ziccamoa) \
+ && defined(__riscv_ziccif) \
+ && defined(__riscv_zicclsm) \
+ && defined(__riscv_ziccrse) \
+ && defined(__riscv_zicntr) \
+ && defined(__riscv_zicond) \
+ && defined(__riscv_zifencei) \
+ && defined(__riscv_zihintntl) \
+ && defined(__riscv_zihintpause) \
+ && defined(__riscv_zihpm) \
+ && defined(__riscv_zimop) \
+ && defined(__riscv_za64rs) \
+ && defined(__riscv_zama16b) \
+ && defined(__riscv_zawrs) \
+ && defined(__riscv_zfa) \
+ && defined(__riscv_zfh) \
+ && defined(__riscv_zcb) \
+ && defined(__riscv_zcmop) \
+ && defined(__riscv_zkr) \
+ && defined(__riscv_zkt) \
+ && defined(__riscv_zvbb) \
+ && defined(__riscv_zvfbfwma) \
+ && defined(__riscv_zvfh) \
+ && defined(__riscv_zvfhmin) \
+ && defined(__riscv_zvknc) \
+ && defined(__riscv_zvksg))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
--
2.53.0
