On Mon, Oct 8, 2012 at 9:36 PM, Marc Glisse <marc.gli...@inria.fr> wrote: > On Mon, 8 Oct 2012, Uros Bizjak wrote: > >> You missed the most important sseadd1 addition, the one that prevents >> checking of operand2 when calculating "memory" attribute: >> >> (and (eq_attr "type" >> "!alu1,negnot,ishift1, >> imov,imovx,icmp,test,bitmanip, >> fmov,fcmp,fsgn, >> >> sse,ssemov,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,sselog1, >> sseiadd1,mmx,mmxmov,mmxcmp,mmxcvt") >> (match_operand 2 "memory_operand")) >> >> Please note "!" in the above expression. > > [...] > >> Also note that you have to add handling of sseadd1 attribute in other >> (scheduler) *.md files. Simply grep for sseadd and add ",sseadd1" >> everywhere. > > > Thank you, it makes more sense now. The attached passed bootstrap+testsuite. > I didn't know if I should be more precise in the ChangeLog, but it would > make the ChangeLog as long as the patch with about 23 entries like: > (define_insn_reservation bdver1_ssemuladd_256): Likewise > > Next goal would be to further recognize some DPPD potential uses, but that > seems harder. > > > 2012-10-09 Marc Glisse <marc.gli...@inria.fr> > > > gcc/ > PR target/54400 > * config/i386/i386.md (type attribute): Add sseadd1. > (unit attribute): Add support for sseadd1. > (memory attribute): Likewise. > * config/i386/athlon.md: Likewise. > * config/i386/core2.md: Likewise. > * config/i386/atom.md: Likewise. > * config/i386/ppro.md: Likewise. > * config/i386/bdver1.md: Likewise. > > * config/i386/sse.md (sse3_h<plusminus_insn>v2df3): split into... > (sse3_haddv2df3): ... expander. > (*sse3_haddv2df3): ... define_insn. Accept permuted operands. > (sse3_hsubv2df3): ... define_insn. > (*sse3_haddv2df3_low): New define_insn. > (*sse3_hsubv2df3_low): New define_insn. > > gcc/testsuite/ > PR target/54400 > * gcc.target/i386/pr54400.c: New testcase.
OK for mainline SVN with a couple of small changes below ... > +(define_insn "*sse3_haddv2df3" > [(set (match_operand:V2DF 0 "register_operand" "=x,x") > (vec_concat:V2DF > - (plusminus:DF > + (plus:DF > + (vec_select:DF > + (match_operand:V2DF 1 "register_operand" "0,x") > + (parallel [(match_operand:SI 3 "const_0_to_1_operand")])) > + (vec_select:DF > + (match_dup 1) > + (parallel [(match_operand:SI 4 "const_0_to_1_operand")]))) > + (plus:DF > + (vec_select:DF > + (match_operand:V2DF 2 "nonimmediate_operand" "xm,xm") > + (parallel [(match_operand:SI 5 "const_0_to_1_operand")])) > + (vec_select:DF > + (match_dup 2) > + (parallel [(match_operand:SI 6 "const_0_to_1_operand")])))))] > + "TARGET_SSE3 && INTVAL (operands[3]) != INTVAL (operands[4]) > + && INTVAL (operands[5]) != INTVAL (operands[6])" Please put every && expression in its own line: "TARGET_SSE3 && INTVAL (operands[3]) != INTVAL (operands[4]) && INTVAL (operands[5]) != INTVAL (operands[6])" > +(define_insn "*sse3_haddv2df3_low" > + [(set (match_operand:DF 0 "register_operand" "=x,x") > + (plus:DF > + (vec_select:DF > + (match_operand:V2DF 1 "register_operand" "0,x") > + (parallel [(match_operand:SI 2 "const_0_to_1_operand")])) > + (vec_select:DF > + (match_dup 1) > + (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))))] > + "TARGET_SSE3 && INTVAL (operands[2]) != INTVAL (operands[3])" Also here. Thanks, Uros.
