CACHE_ALIGNED_STD modeled a Veyron V1 store-commit optimization. That
design will not reach silicon and no upstream tune enables the fusion.
Remove the specialized recognizer and its unused flag.
gcc/ChangeLog:
* config/riscv/riscv-fusion.cc (riscv_fuse_cache_aligned_std):
Remove.
(riscv_fusion_table): Remove its entry.
* config/riscv/riscv-protos.h (enum riscv_fusion_pairs): Remove
RISCV_FUSE_CACHE_ALIGNED_STD.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/fusion-cache-aligned-std.c: Remove.
Signed-off-by: Jin Ma <[email protected]>
---
gcc/config/riscv/riscv-fusion.cc | 65 -------------------
gcc/config/riscv/riscv-protos.h | 7 +-
.../riscv/fusion-cache-aligned-std.c | 21 ------
3 files changed, 3 insertions(+), 90 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/fusion-cache-aligned-std.c
diff --git a/gcc/config/riscv/riscv-fusion.cc b/gcc/config/riscv/riscv-fusion.cc
index ca4de9dfc9e..2ce9b965974 100644
--- a/gcc/config/riscv/riscv-fusion.cc
+++ b/gcc/config/riscv/riscv-fusion.cc
@@ -561,69 +561,6 @@ riscv_fuse_auipc_ld (rtx_insn *prev, rtx_insn *curr)
return false;
}
-/* Check for RISCV_FUSE_CACHE_ALIGNED_STD fusion.
- prev (sd) == (set (mem:DI (rs1, offset1)) (reg:DI rs2))
- curr (sd) == (set (mem:DI (rs1, offset2)) (reg:DI rs3))
-
- Constraints:
- rs1 has at least 128-bit pointer alignment
- min (offset1, offset2) is 16-byte aligned
- abs (offset1 - offset2) == 8. */
-
-static bool
-riscv_fuse_cache_aligned_std (rtx_insn *prev, rtx_insn *curr)
-{
- rtx prev_set = single_set (prev);
- rtx curr_set = single_set (curr);
- if (!prev_set || !curr_set || any_condjump_p (curr))
- return false;
-
- if (MEM_P (SET_DEST (prev_set))
- && MEM_P (SET_DEST (curr_set))
- && SCALAR_INT_MODE_P (GET_MODE (SET_DEST (curr_set)))
- /* We can probably relax this condition. The documentation is a bit
- unclear about sub-word cases. So we just model DImode for now. */
- && GET_MODE (SET_DEST (curr_set)) == DImode
- && GET_MODE (SET_DEST (prev_set)) == DImode)
- {
- rtx base_prev, base_curr, offset_prev, offset_curr;
-
- extract_base_offset_in_addr (SET_DEST (prev_set),
- &base_prev, &offset_prev);
- extract_base_offset_in_addr (SET_DEST (curr_set),
- &base_curr, &offset_curr);
-
- /* Proceed only if we find both bases, both bases are register and
- bases are the same register. */
- if (base_prev != NULL_RTX && base_curr != NULL_RTX
- && REG_P (base_prev) && REG_P (base_curr)
- && REGNO (base_prev) == REGNO (base_curr)
- /* The alignment of the base pointer is more useful than the
- alignment of the memory reference for determining if we're
- on opposite sides of a cache line. */
- && REGNO_POINTER_ALIGN (ORIGINAL_REGNO (base_prev)) >= 128)
- {
- /* The two stores must be contained within opposite halves of
- the same 16 byte aligned block of memory. We know the
- pointer has suitable alignment, so we just need to check
- the offsets of the two stores for suitable alignment. */
-
- /* Get the smaller offset into OFFSET_PREV. */
- if (INTVAL (offset_prev) > INTVAL (offset_curr))
- std::swap (offset_prev, offset_curr);
-
- /* We have a match if the smaller offset (OFFSET_PREV) is 16
- byte aligned and the higher offset is 8 bytes more than
- the lower offset. */
- if ((INTVAL (offset_prev) % 16) == 0
- && (INTVAL (offset_prev) + 8 == INTVAL (offset_curr)))
- return true;
- }
- }
-
- return false;
-}
-
/* Check for RISCV_FUSE_ALIGNED_STD fusion.
prev (store) == (set (mem (rs1, offset1)) (reg rs2))
curr (store) == (set (mem (rs1, offset2)) (reg rs3))
@@ -850,8 +787,6 @@ static const struct riscv_fusion_entry riscv_fusion_table[]
=
riscv_fuse_lui_ld, "RISCV_FUSE_LUI_LD" },
{ RISCV_FUSE_AUIPC_LD,
riscv_fuse_auipc_ld, "RISCV_FUSE_AUIPC_LD" },
- { RISCV_FUSE_CACHE_ALIGNED_STD,
- riscv_fuse_cache_aligned_std, "RISCV_FUSE_CACHE_ALIGNED_STD" },
{ RISCV_FUSE_ALIGNED_STD,
riscv_fuse_aligned_std, "RISCV_FUSE_ALIGNED_STD" },
{ RISCV_FUSE_BFEXT,
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index f23aeacf895..e9612cca1a1 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -863,10 +863,9 @@ enum riscv_fusion_pairs
RISCV_FUSE_AUIPC_LD = HOST_WIDE_INT_1U << 7,
RISCV_FUSE_LDPREINCREMENT = HOST_WIDE_INT_1U << 8,
RISCV_FUSE_ALIGNED_STD = HOST_WIDE_INT_1U << 9,
- RISCV_FUSE_CACHE_ALIGNED_STD = HOST_WIDE_INT_1U << 10,
- RISCV_FUSE_BFEXT = HOST_WIDE_INT_1U << 11,
- RISCV_FUSE_EXPANDED_LD = HOST_WIDE_INT_1U << 12,
- RISCV_FUSE_B_ALUI = HOST_WIDE_INT_1U << 13,
+ RISCV_FUSE_BFEXT = HOST_WIDE_INT_1U << 10,
+ RISCV_FUSE_EXPANDED_LD = HOST_WIDE_INT_1U << 11,
+ RISCV_FUSE_B_ALUI = HOST_WIDE_INT_1U << 12,
};
extern bool riscv_macro_fusion_p (void);
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-cache-aligned-std.c
b/gcc/testsuite/gcc.target/riscv/fusion-cache-aligned-std.c
deleted file mode 100644
index 5484e0c0575..00000000000
--- a/gcc/testsuite/gcc.target/riscv/fusion-cache-aligned-std.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Verify RISCV_FUSE_CACHE_ALIGNED_STD correctly matches consecutive
- stores to the same cache line. This exercises the fix for base
- register comparison (changed from != to ==). */
-/* { dg-do compile } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" "-flto" } } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=sifive-p600-series
-fdump-rtl-sched1" } */
-/* No upstream mtune currently enables RISCV_FUSE_CACHE_ALIGNED_STD. */
-/* { dg-final { scan-rtl-dump "RISCV_FUSE_CACHE_ALIGNED_STD" "sched1" { xfail
*-*-* } } } */
-
-struct pair
-{
- long a;
- long b;
-} __attribute__ ((aligned (16)));
-
-void
-store_pair (struct pair *p, long x, long y)
-{
- p->a = x;
- p->b = y;
-}
--
2.52.0
