Relax register constraint on operand 1 of *bt<mode> from "q" to "r"
so it is no longer restricted to the legacy byte-addressable register
class. Also remove the unneeded "r,m" constraints on operand 0
of *bt<SWI48:mode>_mask pre-reload splitter, keeping only the
nonimmediate_operand predicate.
gcc/ChangeLog:
* config/i386/i386.md (*bt<mode>): Change operand 1 constraint
from "q<S>,<S>" to "r<S>,<S>".
(*bt<SWI48:mode>_mask): Remove constraints from operand 0.
Bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32}.
Uros,
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 73d005ef5ed..4e18797743f 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -20131,7 +20131,7 @@ (define_insn "*bt<mode>"
(zero_extract:SWI48
(match_operand:SWI48 0 "nonimmediate_operand" "r,m")
(const_int 1)
- (match_operand:QI 1 "nonmemory_operand" "q<S>,<S>"))))]
+ (match_operand:QI 1 "nonmemory_operand" "r<S>,<S>"))))]
""
{
switch (get_attr_mode (insn))
@@ -20160,7 +20160,7 @@ (define_insn_and_split "*bt<SWI48:mode>_mask"
(compare:CCC
(const_int 0)
(zero_extract:SWI48
- (match_operand:SWI48 0 "nonimmediate_operand" "r,m")
+ (match_operand:SWI48 0 "nonimmediate_operand")
(const_int 1)
(subreg:QI
(and
