From: Pan Li <[email protected]>
For csrr not asm check when enable overlap enabled.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr112431-44.c: New test.
* gcc.target/riscv/rvv/base/pr112431-45.c: New test.
* gcc.target/riscv/rvv/base/pr112431-46.c: New test.
* gcc.target/riscv/rvv/base/pr112431-47.c: New test.
Signed-off-by: Pan Li <[email protected]>
Co-Authored-By: Claude Opus 5 (1M context) <[email protected]>
---
.../gcc.target/riscv/rvv/base/pr112431-44.c | 56 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/pr112431-45.c | 56 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/pr112431-46.c | 59 +++++++++++++++++++
.../gcc.target/riscv/rvv/base/pr112431-47.c | 59 +++++++++++++++++++
4 files changed, 230 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-44.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-45.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-46.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-47.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-44.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-44.c
new file mode 100644
index 00000000000..528b233e630
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-44.c
@@ -0,0 +1,56 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void
+foo (void *in, void *out, int n)
+{
+ vint8m2_t vs = __riscv_vle8_v_i8m2 (in, 4);in+=100;
+
+ for (int i = 0; i < n; i++)
+ {
+ asm volatile("nop" ::: "memory");
+ vint16m4_t v0 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+ vint8m2_t v0_n = __riscv_vreinterpret_v_i16m2_i8m2
(__riscv_vget_v_i16m4_i16m2 (v0, 1));
+ v0 = __riscv_vwsub_vv_i16m4_tu (v0, v0_n, vs, 4);
+ asm volatile("nop" ::: "memory");
+ vint16m4_t v1 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+ vint8m2_t v1_n = __riscv_vreinterpret_v_i16m2_i8m2
(__riscv_vget_v_i16m4_i16m2 (v1, 1));
+ v1 = __riscv_vwsub_vv_i16m4_tu (v1, v1_n, vs, 4);
+ asm volatile("nop" ::: "memory");
+ vint16m4_t v2 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+ vint8m2_t v2_n = __riscv_vreinterpret_v_i16m2_i8m2
(__riscv_vget_v_i16m4_i16m2 (v2, 1));
+ v2 = __riscv_vwsub_vv_i16m4_tu (v2, v2_n, vs, 4);
+ asm volatile("nop" ::: "memory");
+ vint16m4_t v3 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+ vint8m2_t v3_n = __riscv_vreinterpret_v_i16m2_i8m2
(__riscv_vget_v_i16m4_i16m2 (v3, 1));
+ v3 = __riscv_vwsub_vv_i16m4_tu (v3, v3_n, vs, 4);
+ asm volatile("nop" ::: "memory");
+ vint16m4_t v4 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+ vint8m2_t v4_n = __riscv_vreinterpret_v_i16m2_i8m2
(__riscv_vget_v_i16m4_i16m2 (v4, 1));
+ v4 = __riscv_vwsub_vv_i16m4_tu (v4, v4_n, vs, 4);
+ asm volatile("nop" ::: "memory");
+ vint16m4_t v5 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+ vint8m2_t v5_n = __riscv_vreinterpret_v_i16m2_i8m2
(__riscv_vget_v_i16m4_i16m2 (v5, 1));
+ v5 = __riscv_vwsub_vv_i16m4_tu (v5, v5_n, vs, 4);
+ asm volatile("nop" ::: "memory");
+ vint8m2_t v6_n = __riscv_vle8_v_i8m2 (in, 4);in+=100;
+ vint16m4_t v6 = __riscv_vwcvt_x_x_v_i16m4 (v6_n, 4);
+
+ asm volatile("nop" ::: "memory");
+ __riscv_vsse16_v_i16m4 (out, 4, v0, 4);out+=100;
+ __riscv_vsse16_v_i16m4 (out, 4, v1, 4);out+=100;
+ __riscv_vsse16_v_i16m4 (out, 4, v2, 4);out+=100;
+ __riscv_vsse16_v_i16m4 (out, 4, v3, 4);out+=100;
+ __riscv_vsse16_v_i16m4 (out, 4, v4, 4);out+=100;
+ __riscv_vsse16_v_i16m4 (out, 4, v5, 4);out+=100;
+ __riscv_vsse16_v_i16m4 (out, 4, v6, 4);out+=100;
+ }
+}
+
+/* { dg-final { scan-assembler-not {vmv1r} } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-45.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-45.c
new file mode 100644
index 00000000000..e7967913e8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-45.c
@@ -0,0 +1,56 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void
+foo (void *in, void *out, int n)
+{
+ vuint8m2_t vs = __riscv_vle8_v_u8m2 (in, 4);in+=100;
+
+ for (int i = 0; i < n; i++)
+ {
+ asm volatile("nop" ::: "memory");
+ vuint16m4_t v0 = __riscv_vle16_v_u16m4 (in, 4);in+=100;
+ vuint8m2_t v0_n = __riscv_vreinterpret_v_u16m2_u8m2
(__riscv_vget_v_u16m4_u16m2 (v0, 1));
+ v0 = __riscv_vwsubu_vv_u16m4_tu (v0, v0_n, vs, 4);
+ asm volatile("nop" ::: "memory");
+ vuint16m4_t v1 = __riscv_vle16_v_u16m4 (in, 4);in+=100;
+ vuint8m2_t v1_n = __riscv_vreinterpret_v_u16m2_u8m2
(__riscv_vget_v_u16m4_u16m2 (v1, 1));
+ v1 = __riscv_vwsubu_vv_u16m4_tu (v1, v1_n, vs, 4);
+ asm volatile("nop" ::: "memory");
+ vuint16m4_t v2 = __riscv_vle16_v_u16m4 (in, 4);in+=100;
+ vuint8m2_t v2_n = __riscv_vreinterpret_v_u16m2_u8m2
(__riscv_vget_v_u16m4_u16m2 (v2, 1));
+ v2 = __riscv_vwsubu_vv_u16m4_tu (v2, v2_n, vs, 4);
+ asm volatile("nop" ::: "memory");
+ vuint16m4_t v3 = __riscv_vle16_v_u16m4 (in, 4);in+=100;
+ vuint8m2_t v3_n = __riscv_vreinterpret_v_u16m2_u8m2
(__riscv_vget_v_u16m4_u16m2 (v3, 1));
+ v3 = __riscv_vwsubu_vv_u16m4_tu (v3, v3_n, vs, 4);
+ asm volatile("nop" ::: "memory");
+ vuint16m4_t v4 = __riscv_vle16_v_u16m4 (in, 4);in+=100;
+ vuint8m2_t v4_n = __riscv_vreinterpret_v_u16m2_u8m2
(__riscv_vget_v_u16m4_u16m2 (v4, 1));
+ v4 = __riscv_vwsubu_vv_u16m4_tu (v4, v4_n, vs, 4);
+ asm volatile("nop" ::: "memory");
+ vuint16m4_t v5 = __riscv_vle16_v_u16m4 (in, 4);in+=100;
+ vuint8m2_t v5_n = __riscv_vreinterpret_v_u16m2_u8m2
(__riscv_vget_v_u16m4_u16m2 (v5, 1));
+ v5 = __riscv_vwsubu_vv_u16m4_tu (v5, v5_n, vs, 4);
+ asm volatile("nop" ::: "memory");
+ vuint8m2_t v6_n = __riscv_vle8_v_u8m2 (in, 4);in+=100;
+ vuint16m4_t v6 = __riscv_vwcvtu_x_x_v_u16m4 (v6_n, 4);
+
+ asm volatile("nop" ::: "memory");
+ __riscv_vsse16_v_u16m4 (out, 4, v0, 4);out+=100;
+ __riscv_vsse16_v_u16m4 (out, 4, v1, 4);out+=100;
+ __riscv_vsse16_v_u16m4 (out, 4, v2, 4);out+=100;
+ __riscv_vsse16_v_u16m4 (out, 4, v3, 4);out+=100;
+ __riscv_vsse16_v_u16m4 (out, 4, v4, 4);out+=100;
+ __riscv_vsse16_v_u16m4 (out, 4, v5, 4);out+=100;
+ __riscv_vsse16_v_u16m4 (out, 4, v6, 4);out+=100;
+ }
+}
+
+/* { dg-final { scan-assembler-not {vmv1r} } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-46.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-46.c
new file mode 100644
index 00000000000..32be63ff1a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-46.c
@@ -0,0 +1,59 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void
+foo (void *in, void *out, int n)
+{
+ for (int i = 0; i < n; i++)
+ {
+ asm volatile("nop" ::: "memory");
+ vint16m4_t v0 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+ vint8m2_t v0_n = __riscv_vreinterpret_v_i16m2_i8m2
(__riscv_vget_v_i16m4_i16m2 (v0, 1));
+ v0 = __riscv_vwmul_vv_i16m4_tu (v0, v0_n, v0_n, 4);
+ asm volatile("nop" ::: "memory");
+ vint16m4_t v1 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+ vint8m2_t v1_n = __riscv_vreinterpret_v_i16m2_i8m2
(__riscv_vget_v_i16m4_i16m2 (v1, 1));
+ v1 = __riscv_vwmul_vv_i16m4_tu (v1, v1_n, v1_n, 4);
+ asm volatile("nop" ::: "memory");
+ vint16m4_t v2 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+ vint8m2_t v2_n = __riscv_vreinterpret_v_i16m2_i8m2
(__riscv_vget_v_i16m4_i16m2 (v2, 1));
+ v2 = __riscv_vwmul_vv_i16m4_tu (v2, v2_n, v2_n, 4);
+ asm volatile("nop" ::: "memory");
+ vint16m4_t v3 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+ vint8m2_t v3_n = __riscv_vreinterpret_v_i16m2_i8m2
(__riscv_vget_v_i16m4_i16m2 (v3, 1));
+ v3 = __riscv_vwmul_vv_i16m4_tu (v3, v3_n, v3_n, 4);
+ asm volatile("nop" ::: "memory");
+ vint16m4_t v4 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+ vint8m2_t v4_n = __riscv_vreinterpret_v_i16m2_i8m2
(__riscv_vget_v_i16m4_i16m2 (v4, 1));
+ v4 = __riscv_vwmul_vv_i16m4_tu (v4, v4_n, v4_n, 4);
+ asm volatile("nop" ::: "memory");
+ vint16m4_t v5 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+ vint8m2_t v5_n = __riscv_vreinterpret_v_i16m2_i8m2
(__riscv_vget_v_i16m4_i16m2 (v5, 1));
+ v5 = __riscv_vwmul_vv_i16m4_tu (v5, v5_n, v5_n, 4);
+ asm volatile("nop" ::: "memory");
+ vint16m4_t v6 = __riscv_vle16_v_i16m4 (in, 4);in+=100;
+ vint8m2_t v6_n = __riscv_vreinterpret_v_i16m2_i8m2
(__riscv_vget_v_i16m4_i16m2 (v6, 1));
+ v6 = __riscv_vwmul_vv_i16m4_tu (v6, v6_n, v6_n, 4);
+ asm volatile("nop" ::: "memory");
+ vint8m2_t v7_n = __riscv_vle8_v_i8m2 (in, 4);in+=100;
+ vint16m4_t v7 = __riscv_vwcvt_x_x_v_i16m4 (v7_n, 4);
+
+ asm volatile("nop" ::: "memory");
+ __riscv_vsse16_v_i16m4 (out, 4, v0, 4);out+=100;
+ __riscv_vsse16_v_i16m4 (out, 4, v1, 4);out+=100;
+ __riscv_vsse16_v_i16m4 (out, 4, v2, 4);out+=100;
+ __riscv_vsse16_v_i16m4 (out, 4, v3, 4);out+=100;
+ __riscv_vsse16_v_i16m4 (out, 4, v4, 4);out+=100;
+ __riscv_vsse16_v_i16m4 (out, 4, v5, 4);out+=100;
+ __riscv_vsse16_v_i16m4 (out, 4, v6, 4);out+=100;
+ __riscv_vsse16_v_i16m4 (out, 4, v7, 4);out+=100;
+ }
+}
+
+/* { dg-final { scan-assembler-not {vmv1r} } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-47.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-47.c
new file mode 100644
index 00000000000..1a1c4c39a9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-47.c
@@ -0,0 +1,59 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void
+foo (void *in, void *out, int n)
+{
+ for (int i = 0; i < n; i++)
+ {
+ asm volatile("nop" ::: "memory");
+ vuint16m4_t v0 = __riscv_vle16_v_u16m4 (in, 4);in+=100;
+ vuint8m2_t v0_n = __riscv_vreinterpret_v_u16m2_u8m2
(__riscv_vget_v_u16m4_u16m2 (v0, 1));
+ v0 = __riscv_vwmulu_vv_u16m4_tu (v0, v0_n, v0_n, 4);
+ asm volatile("nop" ::: "memory");
+ vuint16m4_t v1 = __riscv_vle16_v_u16m4 (in, 4);in+=100;
+ vuint8m2_t v1_n = __riscv_vreinterpret_v_u16m2_u8m2
(__riscv_vget_v_u16m4_u16m2 (v1, 1));
+ v1 = __riscv_vwmulu_vv_u16m4_tu (v1, v1_n, v1_n, 4);
+ asm volatile("nop" ::: "memory");
+ vuint16m4_t v2 = __riscv_vle16_v_u16m4 (in, 4);in+=100;
+ vuint8m2_t v2_n = __riscv_vreinterpret_v_u16m2_u8m2
(__riscv_vget_v_u16m4_u16m2 (v2, 1));
+ v2 = __riscv_vwmulu_vv_u16m4_tu (v2, v2_n, v2_n, 4);
+ asm volatile("nop" ::: "memory");
+ vuint16m4_t v3 = __riscv_vle16_v_u16m4 (in, 4);in+=100;
+ vuint8m2_t v3_n = __riscv_vreinterpret_v_u16m2_u8m2
(__riscv_vget_v_u16m4_u16m2 (v3, 1));
+ v3 = __riscv_vwmulu_vv_u16m4_tu (v3, v3_n, v3_n, 4);
+ asm volatile("nop" ::: "memory");
+ vuint16m4_t v4 = __riscv_vle16_v_u16m4 (in, 4);in+=100;
+ vuint8m2_t v4_n = __riscv_vreinterpret_v_u16m2_u8m2
(__riscv_vget_v_u16m4_u16m2 (v4, 1));
+ v4 = __riscv_vwmulu_vv_u16m4_tu (v4, v4_n, v4_n, 4);
+ asm volatile("nop" ::: "memory");
+ vuint16m4_t v5 = __riscv_vle16_v_u16m4 (in, 4);in+=100;
+ vuint8m2_t v5_n = __riscv_vreinterpret_v_u16m2_u8m2
(__riscv_vget_v_u16m4_u16m2 (v5, 1));
+ v5 = __riscv_vwmulu_vv_u16m4_tu (v5, v5_n, v5_n, 4);
+ asm volatile("nop" ::: "memory");
+ vuint16m4_t v6 = __riscv_vle16_v_u16m4 (in, 4);in+=100;
+ vuint8m2_t v6_n = __riscv_vreinterpret_v_u16m2_u8m2
(__riscv_vget_v_u16m4_u16m2 (v6, 1));
+ v6 = __riscv_vwmulu_vv_u16m4_tu (v6, v6_n, v6_n, 4);
+ asm volatile("nop" ::: "memory");
+ vuint8m2_t v7_n = __riscv_vle8_v_u8m2 (in, 4);in+=100;
+ vuint16m4_t v7 = __riscv_vwcvtu_x_x_v_u16m4 (v7_n, 4);
+
+ asm volatile("nop" ::: "memory");
+ __riscv_vsse16_v_u16m4 (out, 4, v0, 4);out+=100;
+ __riscv_vsse16_v_u16m4 (out, 4, v1, 4);out+=100;
+ __riscv_vsse16_v_u16m4 (out, 4, v2, 4);out+=100;
+ __riscv_vsse16_v_u16m4 (out, 4, v3, 4);out+=100;
+ __riscv_vsse16_v_u16m4 (out, 4, v4, 4);out+=100;
+ __riscv_vsse16_v_u16m4 (out, 4, v5, 4);out+=100;
+ __riscv_vsse16_v_u16m4 (out, 4, v6, 4);out+=100;
+ __riscv_vsse16_v_u16m4 (out, 4, v7, 4);out+=100;
+ }
+}
+
+/* { dg-final { scan-assembler-not {vmv1r} } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
--
2.43.0
