New tests verify that integer division and floating point
arithmetic operations are masked, but integer addition is not.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/slp_pred_16.c: New test.
* gcc.target/aarch64/sve/slp_pred_17.c: New test.
* gcc.target/aarch64/sve/slp_pred_18.c: New test.
---
.../gcc.target/aarch64/sve/slp_pred_16.c | 26 ++++++++++++++++++
.../gcc.target/aarch64/sve/slp_pred_17.c | 27 +++++++++++++++++++
.../gcc.target/aarch64/sve/slp_pred_18.c | 24 +++++++++++++++++
3 files changed, 77 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_pred_16.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_pred_17.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_pred_18.c
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_16.c
b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_16.c
new file mode 100644
index 00000000000..751e43853c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_16.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize
--param=aarch64-autovec-preference=sve-only -msve-vector-bits=scalable
-fdump-tree-slp2" } */
+
+#include <stdint.h>
+
+/* Test that floating point arithmetic is masked. */
+
+void
+f (_Float16 *restrict x, _Float16 *restrict y)
+{
+ x[0] += y[0];
+ x[1] += y[1];
+ x[2] += y[2];
+ x[3] += y[3];
+ x[4] += y[4];
+ x[5] += y[5];
+ x[6] += y[6];
+}
+
+/* { dg-final { scan-tree-dump-times {max_mask_[0-9]+ = \.WHILE_ULT \(0, 7, \{
0, \.\.\. \}\)} 1 "slp2" } } */
+/* { dg-final { scan-tree-dump {\.COND_ADD} "slp2" } } */
+
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.h, vl7\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+.h, p[0-7]\/z,
\[x[0-9]+[^]]*\]} 2 } } */
+/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+.h, p[0-7]/m, z[0-9]+.h,
z[0-9]+.h\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+.h, p[0-7],
\[x[0-9]+[^]]*\]} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_17.c
b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_17.c
new file mode 100644
index 00000000000..2178caf88e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_17.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize
--param=aarch64-autovec-preference=sve-only -msve-vector-bits=scalable
-fdump-tree-slp2" } */
+
+#include <stdint.h>
+
+/* Test that integer addition is not masked, but loads and stores are
+ still masked. */
+
+void
+f (int16_t *restrict x, int16_t *restrict y)
+{
+ x[0] += y[0];
+ x[1] += y[1];
+ x[2] += y[2];
+ x[3] += y[3];
+ x[4] += y[4];
+ x[5] += y[5];
+ x[6] += y[6];
+}
+
+/* { dg-final { scan-tree-dump-times {max_mask_[0-9]+ = \.WHILE_ULT \(0, 7, \{
0, \.\.\. \}\)} 1 "slp2" } } */
+/* { dg-final { scan-tree-dump-not {\.COND_ADD} "slp2" } } */
+
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.h, vl7\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+.h, p[0-7]\/z,
\[x[0-9]+[^]]*\]} 2 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+.h, z[0-9]+.h,
z[0-9]+.h\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+.h, p[0-7],
\[x[0-9]+[^]]*\]} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_18.c
b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_18.c
new file mode 100644
index 00000000000..ec2a2d7aac9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_18.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize
--param=aarch64-autovec-preference=sve-only -msve-vector-bits=scalable
-fdump-tree-slp2" } */
+
+#include <stdint.h>
+
+/* Test that integer division is masked. We cannot use a narrower element type
+ such as int16_t with more than four lanes because integer division must be
+ performed as if on the promoted type, which is 32-bit. */
+
+void
+f (int32_t *restrict x, int32_t *restrict y)
+{
+ x[0] /= y[0];
+ x[1] /= y[1];
+ x[2] /= y[2];
+}
+
+/* { dg-final { scan-tree-dump-times {max_mask_[0-9]+ = \.WHILE_ULT \(0, 3, \{
0, \.\.\. \}\)} 1 "slp2" } } */
+/* { dg-final { scan-tree-dump {\.COND_DIV} "slp2" } } */
+
+/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s, vl3\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+.s, p[0-7]\/z,
\[x[0-9]+[^]]*\]} 2 } } */
+/* { dg-final { scan-assembler-times {\tsdiv\tz[0-9]+.s, p[0-7]/m, z[0-9]+.s,
z[0-9]+.s\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+.s, p[0-7],
\[x[0-9]+[^]]*\]} 1 } } */
--
2.43.0
