On Tue, Jul 28, 2026 at 3:44 PM Haochen Jiang <[email protected]> wrote: > > Hi all, > > vdpbf16ps is using 16 bit mask. However, it only take the lower 8 bit > into consideration due to avx512fhalfmaskmode usage in pattern. > > Correct to avx512fmaskmode and remove not used iterators and patterns. > > Bootstraped the regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk > and backport to GCC13/14/15/16? Ok. > > Thx, > Haochen > > gcc/ChangeLog: > > PR target/126429 > * config/i386/sse.md (avx512fmaskhalfmode): Removed. > (avx512f_dpbf16ps_<mode>_maskz): Use avx512fmaskmode instead of > avx512fmaskhalfmode. > (avx512f_dpbf16ps_<mode>_mask): Ditto. > (avx512f_dpbf16ps_<mode><maskz_half_name>): Rename to ... > (avx512f_dpbf16ps_<mode><sd_maskz_name>): ... this. Use > corresponding sd_mask_op4. > * config/i386/subst.md (maskz_half): Remove not used pattern. > > gcc/testsuite/Changelog: > > PR target/126429 > * gcc.target/testsuite/pr126429-1.c: New test. > --- > gcc/config/i386/sse.md | 19 ++++--------------- > gcc/config/i386/subst.md | 13 ------------- > gcc/testsuite/gcc.target/i386/pr126429-1.c | 15 +++++++++++++++ > 3 files changed, 19 insertions(+), 28 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/pr126429-1.c > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 38cdf607935..bd6ce2ac70c 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -1109,17 +1109,6 @@ > (V16SF "hi") (V8SF "qi") (V4SF "qi") > (V8DF "qi") (V4DF "qi") (V2DF "qi")]) > > -;; Mapping of vector modes to corresponding mask half size > -(define_mode_attr avx512fmaskhalfmode > - [(V64QI "SI") (V32QI "HI") (V16QI "QI") > - (V32HI "HI") (V16HI "QI") (V8HI "QI") (V4HI "QI") > - (V16SI "QI") (V8SI "QI") (V4SI "QI") > - (V8DI "QI") (V4DI "QI") (V2DI "QI") > - (V32HF "HI") (V16HF "QI") (V8HF "QI") > - (V32BF "HI") (V16BF "QI") (V8BF "QI") > - (V16SF "QI") (V8SF "QI") (V4SF "QI") > - (V8DF "QI") (V4DF "QI") (V2DF "QI")]) > - > ;; Mapping of vector float modes to an integer mode of the same size > (define_mode_attr sseintvecmode > [(V32HF "V32HI") (V32BF "V32HI") (V16SF "V16SI") (V8DF "V8DI") > @@ -32630,7 +32619,7 @@ > (match_operand:VF1_AVX512VL 1 "register_operand") > (match_operand:<sf_bf16> 2 "register_operand") > (match_operand:<sf_bf16> 3 "register_operand") > - (match_operand:<avx512fmaskhalfmode> 4 "register_operand")] > + (match_operand:<avx512fmaskmode> 4 "register_operand")] > "TARGET_AVX512BF16" > { > emit_insn (gen_avx512f_dpbf16ps_<mode>_maskz_1(operands[0], operands[1], > @@ -32638,7 +32627,7 @@ > DONE; > }) > > -(define_insn "avx512f_dpbf16ps_<mode><maskz_half_name>" > +(define_insn "avx512f_dpbf16ps_<mode><sd_maskz_name>" > [(set (match_operand:VF1_AVX512VL 0 "register_operand" "=v") > (unspec:VF1_AVX512VL > [(match_operand:VF1_AVX512VL 1 "register_operand" "0") > @@ -32646,7 +32635,7 @@ > (match_operand:<sf_bf16> 3 "nonimmediate_operand" "vm")] > UNSPEC_VDPBF16PS))] > "TARGET_AVX512BF16" > - "vdpbf16ps\t{%3, %2, %0<maskz_half_operand4>|%0<maskz_half_operand4>, %2, > %3}") > + "vdpbf16ps\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}") > > (define_insn "avx512f_dpbf16ps_<mode>_mask" > [(set (match_operand:VF1_AVX512VL 0 "register_operand" "=v") > @@ -32657,7 +32646,7 @@ > (match_operand:<sf_bf16> 3 "nonimmediate_operand" "vm")] > UNSPEC_VDPBF16PS) > (match_dup 1) > - (match_operand:<avx512fmaskhalfmode> 4 "register_operand" "Yk")))] > + (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))] > "TARGET_AVX512BF16" > "vdpbf16ps\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}") > > diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md > index 511fd6ad5c2..f917898e4ad 100644 > --- a/gcc/config/i386/subst.md > +++ b/gcc/config/i386/subst.md > @@ -470,19 +470,6 @@ > (match_operand:SI 3 "const48_operand")] > UNSPEC_EMBEDDED_ROUNDING))]) > > -(define_subst_attr "maskz_half_name" "maskz_half" "" "_maskz_1") > -(define_subst_attr "maskz_half_operand4" "maskz_half" "" "%{%5%}%N4") > - > -(define_subst "maskz_half" > - [(set (match_operand:SUBST_V 0) > - (match_operand:SUBST_V 1))] > - "" > - [(set (match_dup 0) > - (vec_merge:SUBST_V > - (match_dup 1) > - (match_operand:SUBST_V 2 "const0_operand") > - (match_operand:<avx512fmaskhalfmode> 3 "register_operand" "Yk")))]) > - > (define_subst_attr "round_zext_name" "round_zext" "_zext" "_round_zext") > (define_subst_attr "round_zext_constraint" "round_zext" "vm" "v") > (define_subst_attr "round_zext_constraint2" "round_zext" "m" "v") > diff --git a/gcc/testsuite/gcc.target/i386/pr126429-1.c > b/gcc/testsuite/gcc.target/i386/pr126429-1.c > new file mode 100644 > index 00000000000..ef84fe14d1c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr126429-1.c > @@ -0,0 +1,15 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mavx512bf16 -mavx512dq" } */ > +/* { dg-final { scan-assembler-not "kmovb" } } */ > + > +#include <immintrin.h> > + > +__m512 dp16ps_mask (__m512 src, __mmask16 k, __m512bh a, __m512bh b) > +{ > + return _mm512_mask_dpbf16_ps (src, k, a, b); > +} > + > +__m512 dp16ps_maskz (__mmask16 k, __m512 src, __m512bh a, __m512bh b) > +{ > + return _mm512_maskz_dpbf16_ps (k, src, a, b); > +} > -- > 2.31.1 >
-- BR, Hongtao
