The 32-bit DImode patterns for and and friends are not split on parisc.
Based on inspection of the assembly code generated for gcc.dg/lower-subreg-1.c,
it better if we let lower subreg split the DImode objects on parisc and
remove the current DImode patterns.
Tested on hppa-unknown-linux-gnu and committed to trunk.
Dave
--
J. David Anglin dave.ang...@nrc-cnrc.gc.ca
National Research Council of Canada (613) 990-0752 (FAX: 952-6602)
2012-10-05 John David Anglin <dave.ang...@nrc-cnrc.gc.ca>
PR rtl-optimization/54739
* config/pa/pa.md: Remove DImode and, not and, ior and xor patterns
for 32-bit targets. Adjust expanders.
Index: config/pa/pa.md
===================================================================
--- config/pa/pa.md (revision 191943)
+++ config/pa/pa.md (working copy)
@@ -5621,24 +5621,10 @@
[(set (match_operand:DI 0 "register_operand" "")
(and:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "and_operand" "")))]
- ""
- "
-{
- /* Both operands must be register operands. */
- if (!TARGET_64BIT && !register_operand (operands[2], DImode))
- FAIL;
-}")
+ "TARGET_64BIT"
+ "")
(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (and:DI (match_operand:DI 1 "register_operand" "%r")
- (match_operand:DI 2 "register_operand" "r")))]
- "!TARGET_64BIT"
- "and %1,%2,%0\;and %R1,%R2,%R0"
- [(set_attr "type" "binary")
- (set_attr "length" "8")])
-
-(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r,r")
(and:DI (match_operand:DI 1 "register_operand" "%?r,0")
(match_operand:DI 2 "and_operand" "rO,P")))]
@@ -5662,15 +5648,6 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
(match_operand:DI 2 "register_operand" "r")))]
- "!TARGET_64BIT"
- "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
- [(set_attr "type" "binary")
- (set_attr "length" "8")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
- (match_operand:DI 2 "register_operand" "r")))]
"TARGET_64BIT"
"andcm %2,%1,%0"
[(set_attr "type" "binary")
@@ -5689,24 +5666,10 @@
[(set (match_operand:DI 0 "register_operand" "")
(ior:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "reg_or_cint_ior_operand" "")))]
- ""
- "
-{
- /* Both operands must be register operands. */
- if (!TARGET_64BIT && !register_operand (operands[2], DImode))
- FAIL;
-}")
+ "TARGET_64BIT"
+ "")
(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ior:DI (match_operand:DI 1 "register_operand" "%r")
- (match_operand:DI 2 "register_operand" "r")))]
- "!TARGET_64BIT"
- "or %1,%2,%0\;or %R1,%R2,%R0"
- [(set_attr "type" "binary")
- (set_attr "length" "8")])
-
-(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r,r")
(ior:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "cint_ior_operand" "M,i")))]
@@ -5754,24 +5717,13 @@
[(set (match_operand:DI 0 "register_operand" "")
(xor:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" "")))]
- ""
- "
-{
-}")
+ "TARGET_64BIT"
+ "")
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
(xor:DI (match_operand:DI 1 "register_operand" "%r")
(match_operand:DI 2 "register_operand" "r")))]
- "!TARGET_64BIT"
- "xor %1,%2,%0\;xor %R1,%R2,%R0"
- [(set_attr "type" "binary")
- (set_attr "length" "8")])
-
-(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
- (xor:DI (match_operand:DI 1 "register_operand" "%r")
- (match_operand:DI 2 "register_operand" "r")))]
"TARGET_64BIT"
"xor %1,%2,%0"
[(set_attr "type" "binary")
