[PATCH v1 1/4] RISC-V: Allow RVV register overlap for vwadd[u].wv

[pan2 . li]

From: Pan Li <pan2...@intel.com>

Like v[sz]ext.vf8, allow the rvv register overlap
for vwadd[u].wv.

gcc/ChangeLog:

        * config/riscv/riscv-v.cc (riscv_v_widen_constraint_ok): Return
        false when wide_mode and mode are same.
        * config/riscv/vector.md: Leverage Wvr constraint.

Signed-off-by: Pan Li <pan2...@intel.com>
---
 gcc/config/riscv/riscv-v.cc |  2 +-
 gcc/config/riscv/vector.md  | 18 +++++++++---------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c4e62cfc372..e19d2375394 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -6520,7 +6520,7 @@ riscv_v_widen_constraint_ok (unsigned int regno, 
machine_mode mode,
   gcc_checking_assert (riscv_vector_mode_p (mode)
                       && riscv_vector_mode_p (wide_mode));
 
-  if (riscv_tuple_mode_p (mode))
+  if (riscv_tuple_mode_p (mode) || wide_mode == mode)
      return false;
 
   unsigned int wide_nregs = riscv_hard_regno_nregs (wide_regno, wide_mode);
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 32c0036ffa4..fd050f8b1f1 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -4216,21 +4216,21 @@ (define_insn 
"@pred_single_widen_sub<any_extend:su><mode>"
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 
 (define_insn "@pred_single_widen_add<any_extend:su><mode>"
-  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr,&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                 "=vr, vr, 
vd, vd")
        (if_then_else:VWEXTI
          (unspec:<VM>
-           [(match_operand:<VM> 1 "vector_mask_operand"           
"vmWc1,vmWc1")
-            (match_operand 5 "vector_length_operand"              "  rvl,  
rvl")
-            (match_operand 6 "const_int_operand"                  "    i,    
i")
-            (match_operand 7 "const_int_operand"                  "    i,    
i")
-            (match_operand 8 "const_int_operand"                  "    i,    
i")
+           [(match_operand:<VM> 1 "vector_mask_operand"           "Wc1,Wc1, 
vm, vm")
+            (match_operand 5 "vector_length_operand"              
"rvl,rvl,rvl,rvl")
+            (match_operand 6 "const_int_operand"                  "  i,  i,  
i,  i")
+            (match_operand 7 "const_int_operand"                  "  i,  i,  
i,  i")
+            (match_operand 8 "const_int_operand"                  "  i,  i,  
i,  i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (plus:VWEXTI
            (any_extend:VWEXTI
-             (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr,   
vr"))
-           (match_operand:VWEXTI 3 "register_operand"             "   vr,   
vr"))
-         (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    
0")))]
+             (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" 
"Wvr,Wvr,Wvr,Wvr"))
+           (match_operand:VWEXTI 3 "register_operand"             " vr, vr, 
vr, vr"))
+         (match_operand:VWEXTI 2 "vector_merge_operand"           " vu,  0, 
vu,  0")))]
   "TARGET_VECTOR"
   "vwadd<any_extend:u>.wv\t%0,%3,%4%p1"
   [(set_attr "type" "viwalu")
-- 
2.43.0