On 09/27/2012 04:59 PM, Vladimir Makarov wrote:
This is the last patch switching on LRA for x86/x86-64. The patch also
contains code deciding when to use spilling general regs into SSE
instead of memory.
2012-09-27 Vladimir Makarov <vmaka...@redhat.com>
* config/i386/i386.h (enum ix86_tune_indices): Add
X86_TUNE_GENERAL_REGS_SSE_SPILL.
(TARGET_GENERAL_REGS_SSE_SPILL): New macro.
* config/i386/i386.c (initial_ix86_tune_features): Set up
X86_TUNE_GENERAL_REGS_SSE_SPILL for m_COREI7 and
m_CORE2I7.
(ix86_lra_p, ix86_register_bank): New functions.
(ix86_secondary_reload): Add NON_Q_REGS, SIREG, DIREG.
(inline_secondary_memory_needed): Change assert.
(ix86_spill_class, ix86_spill_class_mode): New function.
(TARGET_LRA_P, TARGET_REGISTER_BANK, TARGET_SPILL_CLASS): New macros.
(TARGET_SPILL_CLASS_MODE): New macro.
So for the register_bank stuff, aren't we really just defining some kind
of alternate costing model? ie, we can't really get the costs we want
from register classes, but it's dependent on the precise register used.
I guess I'm rethinking if register bank is the right name.
Otherwise it seems reasonable. Looks like there's an extra newline at EOF.
jeff
