On Mon, Sep 17, 2012 at 8:53 AM, Tulio Magno Quites Machado Filho
<tul...@linux.vnet.ibm.com> wrote:
> Add __builtin_ppc_get_timebase and __builtin_ppc_mftb to read the Time
> Base Register on PowerPC.
> They are required by applications that measure time at high frequencies
> with high precision that can't afford a syscall.
> __builtin_ppc_get_timebase returns the 64 bits of the Time Base Register
> while __builtin_ppc_mftb generates only 1 instruction and returns the
> least significant word on 32-bit environments and the whole Time Base value
> on 64-bit.
VSX Built-in Functions):
> Move some built-ins unrelated to Altivec/VSX to the new section.
This is a lot better and a lot closer.
> +(define_insn "rs6000_get_timebase_ppc32"
> + [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
> + (unspec_volatile:DI [(const_int 0)] UNSPECV_GETTB))
> + (clobber (match_scratch:SI 1 "=r"))
> + (clobber (match_scratch:CC 2 "=y"))]
> + "!TARGET_POWERPC64"
> +{
> + if (WORDS_BIG_ENDIAN)
> + if (TARGET_MFCRF)
> + {
> + return "mfspr %0, 269\;"
> + "mfspr %L0, 268\;"
> + "mfspr %1, 269\;"
> + "cmpw %0,%1\;"
> + "bne- $-16";
> + }
> + else
> + {
> + return "mftbu %0\;"
> + "mftb %L0\;"
> + "mftbu %1\;"
> + "cmpw %0,%1\;"
> + "bne- $-16";
> + }
> + else
> + if (TARGET_MFCRF)
> + {
> + return "mfspr %L0, 269\;"
> + "mfspr %0, 268\;"
> + "mfspr %1, 269\;"
> + "cmpw %L0,%1\;"
> + "bne- $-16";
> + }
> + else
> + {
> + return "mftbu %L0\;"
> + "mftb %0\;"
> + "mftbu %1\;"
> + "cmpw %L0,%1\;"
> + "bne- $-16";
> + }
> +})
When Segher said to use "=y" for the condition register to generalize
the code so that it does not always allocate CR0, it also needs
reference the specific condition register field in the emitted
assembly. You need to tell the processor which CR field the compiler
think is assigned and clobbered.
Thanks, David
