On Wed, Feb 25, 2026 at 11:59:41AM +0000, Srinath Parvathaneni wrote:
> This patch adds support for "+poe2", "+tev", "+tlbid", "+gcie"
> and "+mpamv2" options to enable the architectural extensions
> FEAT_POE2, FEAT_TEV, FEAT_TLBID, FEAT_GCIE and FEAT_MPAMv2
> respectively.
>
> Regression tested on aarch64-none-elf and aarch64-linux-gnu
> and found no regressions.
>
> Ok for master?
We should add the other new architecture options as well, so that we can
support passing the new options to the assembler via the GCC driver. It
probably makes sense to include them all in the same patch.
Note that we can't yet add support for native feature detection, because the
hwcap strings haven't been added to the kernel yet (and won't be until after
the GCC release). This shouldn't cause any problems for now, but if we want to
backport any cpu definitions that include those features in future then we'll
need to backport those strings as well.
Alice
>
> Regards,
> Srinath
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-option-extensions.def (poe2):
> New CLI extension option.
> (tev): Likewise.
> (tlbid): Likewise.
> (gcie): Likewise.
> (mpamv2): Likewise.
> * doc/invoke.texi (poe2): Document option.
> (tev): Likewise.
> (tlbid): Likewise.
> (gcie): Likewise.
> (mpamv2): Likewise.
>
> gcc/testsuite/ChangeLog:
>
> * lib/target-supports.exp
> (check_effective_target_aarch64_poe2_tev_support_ok): Add new target
> check.
> * gcc.target/aarch64/asm-arch-features-2025.c: New test.
> ---
> .../aarch64/aarch64-option-extensions.def | 10 +++++
> gcc/doc/invoke.texi | 10 +++++
> .../aarch64/asm-arch-features-2025.c | 42 +++++++++++++++++++
> gcc/testsuite/lib/target-supports.exp | 14 +++++++
> 4 files changed, 76 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-arch-features-2025.c
>
> diff --git a/gcc/config/aarch64/aarch64-option-extensions.def
> b/gcc/config/aarch64/aarch64-option-extensions.def
> index b5e4b062bed..db7da574585 100644
> --- a/gcc/config/aarch64/aarch64-option-extensions.def
> +++ b/gcc/config/aarch64/aarch64-option-extensions.def
> @@ -351,6 +351,16 @@ AARCH64_OPT_EXTENSION("pcdphint", PCDPHINT, (), (), (),
> "")
>
> AARCH64_OPT_EXTENSION("pops", PoPS, (), (), (), "")
>
> +AARCH64_OPT_EXTENSION("poe2", POE2, (), (), (), "")
> +
> +AARCH64_OPT_EXTENSION("tev", TEV, (), (), (), "")
> +
> +AARCH64_OPT_EXTENSION("tlbid", TLBID, (), (), (), "")
> +
> +AARCH64_OPT_EXTENSION("gcie", GCIE, (), (), (), "")
> +
> +AARCH64_OPT_EXTENSION("mpamv2", MPAMv2, (), (), (), "")
> +
> #undef AARCH64_OPT_FMV_EXTENSION
> #undef AARCH64_OPT_EXTENSION
> #undef AARCH64_OPT_EXTENSION_ALIAS
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index ad4d2e645d1..b4d178d8a93 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -21939,6 +21939,16 @@ Enable the SVE non-widening brain floating-point
> (@code{bf16}) extension.
> This only has an effect when @code{sve2} or @code{sme2} are also enabled.
> @item sve-bfscale
> Enable the SVE_BFSCALE extension.
> +@item poe2
> +Enable the Permission Overlays Extension 2.
> +@item tev
> +Enable the TIndex Exception-like Vector Extension.
> +@item tlbid
> +Enable the TLBI Domains Extension.
> +@item gcie
> +Enable the GICv5 (Generic Interrupt Controller) CPU Interface Extension.
> +@item mpamv2
> +Enable MPAMv2 system registers.
> @end table
>
> Feature @option{crypto} implies @option{aes}, @option{sha2}, and
> @option{simd},
> diff --git a/gcc/testsuite/gcc.target/aarch64/asm-arch-features-2025.c
> b/gcc/testsuite/gcc.target/aarch64/asm-arch-features-2025.c
> new file mode 100644
> index 00000000000..c8e8efec70c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/asm-arch-features-2025.c
> @@ -0,0 +1,42 @@
> +/* { dg-do assemble { target elf } } */
> +/* { dg-require-effective-target aarch64_arch2025_support_ok } */
> +/* { dg-additional-options "-march=armv8-a+poe2+tev+tlbid+gcie+mpamv2
> --save-temps" } */
> +/* Ensure -march=armv8-a+poe2+tev+tlbid+gcie+mpamv2 is passed to the
> assembler
> + and that the test runs only when those features are supported by the
> + assembler. */
> +
> +void
> +poe2_test ()
> +{
> + __asm__ __volatile__ ("tchangef x0, x1\n" :::"memory");
> +}
> +
> +void
> +tev_test ()
> +{
> + __asm__ __volatile__ ("texit\t" :::"memory");
> +}
> +
> +void
> +tlbi_test ()
> +{
> + __asm__ __volatile__ ("tlbi alle1is, x0\n" :::"memory");
> +}
> +
> +void
> +gcie_test ()
> +{
> + __asm__ __volatile__ ("msr icc_apr_el1, x0\n" :::"memory");
> +}
> +
> +void
> +mpamv2_test ()
> +{
> + __asm__ __volatile__ ("mlbi vmalle1\n" :::"memory");
> +}
> +
> +/* { dg-final { scan-assembler {\ttchangef x0, x1} } } */
> +/* { dg-final { scan-assembler {\ttexit} } } */
> +/* { dg-final { scan-assembler {\ttlbi alle1is, x0} } } */
> +/* { dg-final { scan-assembler {\tmsr icc_apr_el1, x0} } } */
> +/* { dg-final { scan-assembler {\tmlbi vmalle1} } } */
> diff --git a/gcc/testsuite/lib/target-supports.exp
> b/gcc/testsuite/lib/target-supports.exp
> index 212ec081e99..d6b678c22c7 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -12777,6 +12777,20 @@ proc
> check_effective_target_aarch64_sysreg_guarding_ok { } {
> }
> }
>
> +proc check_effective_target_aarch64_arch2025_support_ok { } {
> + if { [istarget aarch64*-*-*] && [check_effective_target_elf] } {
> + return [check_no_compiler_messages aarch64_assembler object {
> + __asm__ ("tchangef x0, x1");
> + __asm__ ("texit");
> + __asm__ ("tlbi alle1is, x0");
> + __asm__ ("mlbi vmalle1");
> + __asm__ ("msr icc_apr_el1, x0");
> + } "-march=armv8-a+poe2+tev+tlbid+mpamv2+gcie"]
> + } else {
> + return 0
> + }
> +}
> +
> proc check_effective_target_aarch64_asm_sve2p1_ok { } {
> if { [istarget aarch64*-*-*] } {
> return [check_no_compiler_messages aarch64_sve2p1_assembler object {
> --
> 2.25.1
>
