[PATCH] i386: Fix up avx512fp16_mov AVX10.2 operand order for -masm=intel [PR124294]

[Jakub Jelinek]

Hi!

This insn uses incorrect operand order for -masm=intel in the AVX10.2
variant.
I've checked for similar mistakes and haven't found any in all the i386/*.md
files.

Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk/15.3?

Note, I also wonder why the insn doesn't use * in front of the define_insn
name, I can't find anything that would need gen_avx512fp16_movv8{hi,hf,bf}.

2026-03-02  Jakub Jelinek  <ja...@redhat.com>

        PR target/124294
        * config/i386/sse.md (avx512fp16_mov<mode>): Fix ordering of operands
        for -masm=intel for the avx10_2 alternative.  Fix up indentation in
        the insn condition.
        (vec_set<mode>_0): Fix comment typo, higer -> higher.

        * gcc.target/i386/avx10_2-pr124294.c: New test.

--- gcc/config/i386/sse.md.jj   2026-03-02 07:43:12.331788314 +0100
+++ gcc/config/i386/sse.md      2026-03-02 10:21:03.318657689 +0100
@@ -12377,7 +12377,7 @@ (define_insn_and_split "*vec_set<mode>_0
   operands[2] = gen_lowpart (<ssescalarmode>mode, operands[2]);
 })
 
-;; vmovw clears also the higer bits
+;; vmovw clears also the higher bits
 (define_insn "vec_set<mode>_0"
   [(set (match_operand:VI2F_256_512 0 "register_operand" "=v,v,v")
        (vec_merge:VI2F_256_512
@@ -12442,10 +12442,10 @@ (define_insn "avx512fp16_mov<mode>"
          (match_operand:V8_128 1 "reg_or_0_operand" "v,C")
          (const_int 1)))]
   "TARGET_AVX512FP16
-  || (TARGET_AVX10_2 && const0_operand (operands[1], <MODE>mode))"
+   || (TARGET_AVX10_2 && const0_operand (operands[1], <MODE>mode))"
   "@
     vmovsh\t{%2, %1, %0|%0, %1, %2}
-    vmovw\t{%2, %0|%2, %0}"
+    vmovw\t{%2, %0|%0, %2}"
   [(set_attr "isa" "*,avx10_2")
    (set_attr "type" "ssemov")
    (set_attr "prefix" "evex")
--- gcc/testsuite/gcc.target/i386/avx10_2-pr124294.c.jj 2026-03-02 
10:24:04.887620795 +0100
+++ gcc/testsuite/gcc.target/i386/avx10_2-pr124294.c    2026-03-02 
10:23:29.871206473 +0100
@@ -0,0 +1,14 @@
+/* PR target/124294 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx10.2 -masm=intel" } */
+/* { dg-require-effective-target masm_intel } */
+/* { dg-final { scan-assembler "\tvmovw\txmm0, xmm1" } } */
+
+typedef unsigned char V __attribute__((vector_size (16)));
+
+V
+foo (V x, V y)
+{
+  (void) x;
+  return __builtin_shuffle (y, (V) {}, (V) { 0, 1, 18, 19, 20, 21, 22, 23, 24, 
25, 26, 27, 28, 29, 30, 31 });
+}

        Jakub