When the most significant bit of the 13 bit immediate value in LoongArch
{x}vldi isntruction is set 1, it can generate different numbers based on
the algorithm. This patch adds to support these numbers to be
generated by {x}vldi instruction.
gcc/ChangeLog:
* config/loongarch/constraints.md: Update constraint YI to support
more numbers.
* config/loongarch/loongarch-protos.h
(loongarch_const_vector_vrepli): Rename.
(loongarch_const_vector_vldi): Ditto.
* config/loongarch/loongarch.cc (VLDI_NEG_MASK): New macro.
(loongarch_parse_vldi_const): New function to check if numbers can
be generated by {x}vldi instruction.
(loongarch_const_vector_vrepli): Rename.
(loongarch_const_vector_vldi): Use above function.
(loongarch_const_insns): Call renamed function.
(loongarch_split_vector_move_p): Ditto.
(loongarch_output_move): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lasx/lasx-builtin.c: Replace xvrepli
with xvldi.
* gcc.target/loongarch/vector/lasx/lasx-vec-init-2.c: Fix test.
* gcc.target/loongarch/vector/lsx/lsx-builtin.c: Repalce vrepli with
vldi.
* gcc.target/loongarch/vrepli.c: Ditto.
* gcc.target/loongarch/vector/lasx/lasx-xvldi-2.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vldi-2.c: New test.
---
gcc/config/loongarch/constraints.md | 5 +-
gcc/config/loongarch/loongarch-protos.h | 2 +-
gcc/config/loongarch/loongarch.cc | 181 +++++++++++++++++-
.../loongarch/vector/lasx/lasx-builtin.c | 8 +-
.../loongarch/vector/lasx/lasx-vec-init-2.c | 2 +-
.../loongarch/vector/lasx/lasx-xvldi-2.c | 97 ++++++++++
.../loongarch/vector/lsx/lsx-builtin.c | 8 +-
.../loongarch/vector/lsx/lsx-vldi-2.c | 93 +++++++++
gcc/testsuite/gcc.target/loongarch/vrepli.c | 4 +-
9 files changed, 377 insertions(+), 23 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldi-2.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vldi-2.c
diff --git a/gcc/config/loongarch/constraints.md
b/gcc/config/loongarch/constraints.md
index 97a4e4e35d3..82bf1d80b1f 100644
--- a/gcc/config/loongarch/constraints.md
+++ b/gcc/config/loongarch/constraints.md
@@ -298,10 +298,9 @@ (define_constraint "Yy"
(define_constraint "YI"
"@internal
- A replicated vector const in which the replicated value is in the range
- [-512,511]."
+ A vector const can be generated by vldi or xvldi instruction."
(and (match_code "const_vector")
- (match_test "loongarch_const_vector_vrepli (op, mode)")))
+ (match_test "loongarch_const_vector_vldi (op, mode)")))
(define_constraint "YC"
"@internal
diff --git a/gcc/config/loongarch/loongarch-protos.h
b/gcc/config/loongarch/loongarch-protos.h
index ffcfa97092a..8301c16c4ef 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -124,7 +124,7 @@ extern bool loongarch_const_vector_shuffle_set_p (rtx,
machine_mode);
extern bool loongarch_const_vector_bitimm_set_p (rtx, machine_mode);
extern bool loongarch_const_vector_bitimm_clr_p (rtx, machine_mode);
extern bool loongarch_check_vect_par_cnst_half (rtx, machine_mode, bool);
-extern rtx loongarch_const_vector_vrepli (rtx, machine_mode);
+extern rtx loongarch_const_vector_vldi (rtx, machine_mode);
extern rtx loongarch_lsx_vec_parallel_const_half (machine_mode, bool);
extern rtx loongarch_gen_const_int_vector (machine_mode, HOST_WIDE_INT);
extern enum reg_class loongarch_secondary_reload_class (enum reg_class,
diff --git a/gcc/config/loongarch/loongarch.cc
b/gcc/config/loongarch/loongarch.cc
index 1f29de5f6e1..5f098208e43 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -1941,8 +1941,170 @@ loongarch_check_vect_par_cnst_half (rtx op,
machine_mode mode, bool high_p)
return true;
}
+/* VLDI or XVLDI instruction could have 13 bits imm part, this mask is used to
+ indicate the highest bit is 1. */
+#define VLDI_NEG_MASK HOST_WIDE_INT_UC(0xFFFFFFFFFFFFF000)
+
+/* Return true if repeated value in vector for machine mode can be set by VLDI
+ or XVLDI instruction, the immediate value for VLDI or XVLDI will be put into
+ res. */
+static bool
+loongarch_parse_vldi_const (rtx op, machine_mode mode,
+ unsigned HOST_WIDE_INT *res)
+{
+ if (!loongarch_const_vector_same_val_p (op, mode))
+ return false;
+
+ rtx elem0 = CONST_VECTOR_ELT (op, 0);
+ if (!CONST_INT_P (elem0))
+ return false;
+
+ HOST_WIDE_INT value = INTVAL (elem0);
+ switch (mode)
+ {
+ case E_V16QImode:
+ case E_V32QImode:
+ {
+ *res = value & 0xFF;
+ return true;
+ }
+ case E_V8HImode:
+ case E_V16HImode:
+ {
+ if (value >= -512 && value <= 511)
+ {
+ *res = 0x400 | (value & 0x3FF);
+ return true;
+ }
+
+ uint16_t num = value & 0xFFFF;
+ /* 4'b0101:data={4{x[7:0],8'b0}}. */
+ if ((num & 0xFF) == 0)
+ {
+ *res = VLDI_NEG_MASK | 0x500 | (num >> 8);
+ return true;
+ }
+ break;
+ }
+ case E_V4SImode:
+ case E_V8SImode:
+ {
+ if (value >= -512 && value <= 511)
+ {
+ *res = 0x800 | (value & 0x3FF);
+ return true;
+ }
+ uint32_t num = value & 0xFFFFFFFF;
+ /* 4'b0001:data={2{16'b0,x[7:0],8'b0}}. */
+ if ((num & 0xFFFF00FF) == 0)
+ {
+ *res = VLDI_NEG_MASK | 0x100 | ((num >> 8) & 0xFF);
+ return true;
+ }
+
+ /* 4'b0010:data={2{8'b0,x[7:0],16'b0}}. */
+ if ((num & 0xFF00FFFF) == 0)
+ {
+ *res = VLDI_NEG_MASK | 0x200 | ((num >> 16) & 0xFF);
+ return true;
+ }
+
+ /* 4'b0011:data={2{x[7:0],24'b0}}. */
+ if ((num & 0xFFFFFF) == 0)
+ {
+ *res = VLDI_NEG_MASK | 0x300 | ((num >> 24) & 0xFF);
+ return true;
+ }
+
+ /* 4'b0110:data={2{16'b0,x[7:0],8'hFF}}. */
+ if (num >> 16 == 0 && (num & 0xFF) == 0xFF)
+ {
+ *res = VLDI_NEG_MASK | 0x600 | ((num >> 8) & 0xFF);
+ return true;
+ }
+
+ /* 4'b0111:data={2{8'b0,x[7:0],16'hFFFF}}. */
+ if (num >> 24 == 0 && (num & 0xFFFF) == 0xFFFF)
+ {
+ *res = VLDI_NEG_MASK | 0x700 | ((num >> 16) & 0xFF);
+ return true;
+ }
+
+ /* 4'b1010:data={2{x[7],~x[6],{5{x[6]}},x[5:0],19'b0}}. */
+ uint32_t temp = (num >> 25) & 0x3F;
+ /* x[6] == 0, then ~x[6],{5{x[6]}} should be 0b10 0000,
+ x[6] == 1, then ~x[6],{5{x[6]}} should be 0b01 1111. */
+ if ((temp == 0x20 || temp == 0x1F) && (num & 0x7FFFF) == 0)
+ {
+ temp = ((num >> 19) & 0x7F) | ((num >> 24) & 0x80);
+ *res = VLDI_NEG_MASK | 0xa00 | temp;
+ return true;
+ }
+ break;
+ }
+ case E_V2DImode:
+ case E_V4DImode:
+ {
+ if (value >= -512 && value <= 511)
+ {
+ *res = 0xC00 | (value & 0x3FF);
+ return true;
+ }
+
+ uint64_t num = value;
+ /* 4'b1001:data={{8{x[7]}},{8{x[6]}},{8{x[5]}},{8{x[4]}},{8{x[3]}},
+ {8{x[2]}},{8{x[1]}},{8{x[0]}}}. */
+ bool same_bit = true;
+ uint64_t temp = 0;
+ for (int i = 0; i < 8; i++)
+ {
+ uint8_t n = (num >> (i * 8)) & 0xFF;
+ if (n != 0 && n != 0xFF)
+ {
+ same_bit = false;
+ break;
+ }
+
+ if (n == 0xFF)
+ temp = (1 << i) | temp;
+ }
+ if (same_bit)
+ {
+ *res = VLDI_NEG_MASK | 0x900 | temp;
+ return true;
+ }
+
+ /* 4'b1011:data={32'b0,x[7],~x[6],{5{x[6]}},x[5:0],19'b0}. */
+ temp = (num >> 25) & 0x3F;
+ if ((num & 0xFFFFFFFF) == num
+ && (temp == 0x20 || temp == 0x1F)
+ && (num & 0x7FFFF) == 0)
+ {
+ temp = ((num >> 19) & 0x7F) | ((num >> 24) & 0x80);
+ *res = VLDI_NEG_MASK | 0xB00 | temp;
+ return true;
+ }
+
+ /* 4'b1100:data={x[7],~x[6],{8{x[6]}},x[5:0],48'b0}. */
+ temp = (num >> 54) & 0x1FF;
+ if ((num & HOST_WIDE_INT_UC(0xFFFF000000000000)) == num
+ && (temp == 0xFF || temp == 0x100))
+ {
+ temp = ((num >> 48) & 0x7F) | ((num >> 56) & 0x80);
+ *res = VLDI_NEG_MASK | 0xC00 | temp;
+ return true;
+ }
+ break;
+ }
+ default:
+ break;
+ }
+
+ return false;
+}
+
rtx
-loongarch_const_vector_vrepli (rtx x, machine_mode mode)
+loongarch_const_vector_vldi (rtx x, machine_mode mode)
{
int size = GET_MODE_SIZE (mode);
@@ -1956,8 +2118,11 @@ loongarch_const_vector_vrepli (rtx x, machine_mode mode)
mode_for_vector (elem_mode, size / GET_MODE_SIZE (elem_mode))
.require ();
rtx op = lowpart_subreg (new_mode, x, mode);
- if (loongarch_const_vector_same_int_p (op, new_mode, -512, 511))
- return op;
+
+ HOST_WIDE_INT res = 0;
+ if (loongarch_parse_vldi_const (op, new_mode,
+ (unsigned HOST_WIDE_INT *)&res))
+ return GEN_INT (res);
}
return NULL_RTX;
@@ -2625,7 +2790,7 @@ loongarch_const_insns (rtx x)
case CONST_VECTOR:
if ((LSX_SUPPORTED_MODE_P (GET_MODE (x))
|| LASX_SUPPORTED_MODE_P (GET_MODE (x)))
- && loongarch_const_vector_vrepli (x, GET_MODE (x)))
+ && loongarch_const_vector_vldi (x, GET_MODE (x)))
return 1;
/* Fall through. */
case CONST_DOUBLE:
@@ -4884,7 +5049,7 @@ loongarch_split_vector_move_p (rtx dest, rtx src)
/* Check for vector set to an immediate const vector with valid replicated
element. */
if (FP_REG_RTX_P (dest)
- && loongarch_const_vector_vrepli (src, GET_MODE (src)))
+ && loongarch_const_vector_vldi (src, GET_MODE (src)))
return false;
/* Check for vector load zero immediate. */
@@ -5020,15 +5185,15 @@ loongarch_output_move (rtx *operands)
&& src_code == CONST_VECTOR
&& CONST_INT_P (CONST_VECTOR_ELT (src, 0)))
{
- operands[1] = loongarch_const_vector_vrepli (src, mode);
+ operands[1] = loongarch_const_vector_vldi (src, mode);
gcc_assert (operands[1]);
switch (GET_MODE_SIZE (mode))
{
case 16:
- return "vrepli.%v1\t%w0,%E1";
+ return "vldi\t%w0,%1";
case 32:
- return "xvrepli.%v1\t%u0,%E1";
+ return "xvldi\t%u0,%1";
default: gcc_unreachable ();
}
}
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c
b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c
index 3f34a430c4e..b9753f5aecb 100644
--- a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c
@@ -733,10 +733,10 @@
/* { dg-final { scan-assembler-times
"lasx_xvfcmp_sun_s:.*xvfcmp\\.sun\\.s.*lasx_xvfcmp_sun_s" 1 } } */
/* { dg-final { scan-assembler-times
"lasx_xvpickve_d_f:.*xvpickve\\.d.*lasx_xvpickve_d_f" 1 } } */
/* { dg-final { scan-assembler-times
"lasx_xvpickve_w_f:.*xvpickve\\.w.*lasx_xvpickve_w_f" 1 } } */
-/* { dg-final { scan-assembler-times
"lasx_xvrepli_b:.*xvrepli\\.b.*lasx_xvrepli_b" 1 } } */
-/* { dg-final { scan-assembler-times
"lasx_xvrepli_d:.*xvrepli\\.d.*lasx_xvrepli_d" 1 } } */
-/* { dg-final { scan-assembler-times
"lasx_xvrepli_h:.*xvrepli\\.h.*lasx_xvrepli_h" 1 } } */
-/* { dg-final { scan-assembler-times
"lasx_xvrepli_w:.*xvrepli\\.w.*lasx_xvrepli_w" 1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvrepli_b:.*xvldi.*lasx_xvrepli_b"
1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvrepli_d:.*xvldi.*lasx_xvrepli_d"
1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvrepli_h:.*xvldi.*lasx_xvrepli_h"
1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvrepli_w:.*xvldi.*lasx_xvrepli_w"
1 } } */
typedef signed char v32i8 __attribute__ ((vector_size (32), aligned (32)));
typedef signed char v32i8_b __attribute__ ((vector_size (32), aligned (1)));
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-init-2.c
b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-init-2.c
index 7592198c448..f0e131f5599 100644
--- a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-init-2.c
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-vec-init-2.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O3 -fno-vect-cost-model -mlasx" } */
-/* { dg-final { scan-assembler-times "vld" 12 } } */
+/* { dg-final { scan-assembler-times "vld\t" 12 } } */
typedef char v16qi __attribute__ ((vector_size (16)));
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldi-2.c
b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldi-2.c
new file mode 100644
index 00000000000..45b596fff40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldi-2.c
@@ -0,0 +1,97 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlasx" } */
+
+#include <lasxintrin.h>
+
+#define TEST_V16I16(imm) \
+void \
+test_v16i16_##imm (v16i16 *vec) \
+ { \
+ v16i16 temp = {imm, imm, imm, imm, \
+ imm, imm, imm, imm, \
+ imm, imm, imm, imm, \
+ imm, imm, imm, imm}; \
+ *vec = temp; \
+ }
+
+#define TEST_V8I32(imm) \
+void \
+test_v8i32_##imm (v8i32 *vec) \
+ { \
+ v8i32 temp = {imm, imm, imm, imm, \
+ imm, imm, imm, imm}; \
+ *vec = temp; \
+ }
+
+#define TEST_V8I32_2(imm1, imm2) \
+void \
+test_v8i32_2_##imm1 (v8i32 *vec) \
+ { \
+ v8i32 temp = {imm1, imm2, imm1, imm2, \
+ imm1, imm2, imm1, imm2};\
+ *vec = temp; \
+ }
+
+#define TEST_V4I64(imm) \
+void \
+test_V4I64_##imm (v4i64 *vec) \
+ { \
+ v4i64 temp = {imm, imm, imm, imm}; \
+ *vec = temp; \
+ }
+
+/* 4'b0001:data={2{16'b0,x[7:0],8'b0}}. */
+TEST_V8I32 (0x3a00)
+/* { dg-final { scan-assembler-times
"test_v8i32_0x3a00:.*\txvldi\t\\\$xr\[0-9\]+,-3782.*-test_v8i32_0x3a00" 1 } } */
+
+/* 4'b0010:data={2{8'b0,x[7:0],16'b0}}. */
+TEST_V8I32 (0x3a0000)
+/* { dg-final { scan-assembler-times
"test_v8i32_0x3a0000:.*\txvldi\t\\\$xr\[0-9\]+,-3526.*-test_v8i32_0x3a0000" 1 }
} */
+
+/* 4'b0011:data={2{x[7:0],24'b0}}. */
+TEST_V8I32 (0x3a000000)
+/* { dg-final { scan-assembler-times
"test_v8i32_0x3a000000:.*\txvldi\t\\\$xr\[0-9\]+,-3270.*-test_v8i32_0x3a000000"
1 } } */
+
+/* 4'b0101:data={4{x[7:0],8'b0}}. */
+TEST_V16I16 (0x3a00)
+/* { dg-final { scan-assembler-times
"test_v16i16_0x3a00:.*\txvldi\t\\\$xr\[0-9\]+,-2758.*-test_v16i16_0x3a00" 1 } }
*/
+
+/* 4'b0110:data={2{16'b0,x[7:0],8'hFF}}. */
+TEST_V8I32 (0x3aff)
+/* { dg-final { scan-assembler-times
"test_v8i32_0x3aff:.*\txvldi\t\\\$xr\[0-9\]+,-2502.*-test_v8i32_0x3aff" 1 } } */
+
+/* 4'b0111:data={2{8'b0,x[7:0],16'hFFFF}}. */
+TEST_V8I32 (0x3affff)
+/* { dg-final { scan-assembler-times
"test_v8i32_0x3affff:.*\txvldi\t\\\$xr\[0-9\]+,-2246.*-test_v8i32_0x3affff" 1 }
} */
+
+/* 4'b1001:data={{8{x[7]}},{8{x[6]}},{8{x[5]}},{8{x[4]}},{8{x[3]}},{8{x[2]}},
+ * {8{x[1]}},{8{x[0]}}}. */
+TEST_V4I64 (0xffffff0000ffff00)
+/* { dg-final { scan-assembler-times
"test_V4I64_0xffffff0000ffff00:.*\txvldi\t\\\$xr\[0-9\]+,-1562.*-test_V4I64_0xffffff0000ffff00"
1 } } */
+
+TEST_V4I64 (0xffff0000ff)
+/* { dg-final { scan-assembler-times
"test_V4I64_0xffff0000ff:.*\txvldi\t\\\$xr\[0-9\]+,-1767.*-test_V4I64_0xffff0000ff"
1 } } */
+
+TEST_V8I32_2 (0xffffff00, 0);
+/* { dg-final { scan-assembler-times
"test_v8i32_2_0xffffff00:.*\txvldi\t\\\$xr\[0-9\]+,-1778.*-test_v8i32_2_0xffffff00"
1 } } */
+
+/* 4'b1010:data={2{x[7],~x[6],{5{x[6]}},x[5:0],19'b0}}. */
+TEST_V8I32 (0xbf180000)
+/* { dg-final { scan-assembler-times
"test_v8i32_0xbf180000:.*\txvldi\t\\\$xr\[0-9\]+,-1309.*-test_v8i32_0xbf180000"
1 } } */
+
+TEST_V8I32 (0x41e00000)
+/* { dg-final { scan-assembler-times
"test_v8i32_0x41e00000:.*\txvldi\t\\\$xr\[0-9\]+,-1476.*-test_v8i32_0x41e00000"
1 } } */
+
+/* 4'b1011:data={32'b0,x[7],~x[6],{5{x[6]}},x[5:0],19'b0}. */
+TEST_V4I64 (0xbe180000)
+/* { dg-final { scan-assembler-times
"test_V4I64_0xbe180000:.*\txvldi\t\\\$xr\[0-9\]+,-1085.*-test_V4I64_0xbe180000"
1 } } */
+
+TEST_V4I64 (0x41e00000)
+/* { dg-final { scan-assembler-times
"test_V4I64_0x41e00000:.*\txvldi\t\\\$xr\[0-9\]+,-1220.*-test_V4I64_0x41e00000"
1 } } */
+
+/* 4'b1100:data={x[7],~x[6],{8{x[6]}},x[5:0],48'b0}. */
+TEST_V4I64 (0xbfd5000000000000)
+/* { dg-final { scan-assembler-times
"test_V4I64_0xbfd5000000000000:.*\txvldi\t\\\$xr\[0-9\]+,-811.*-test_V4I64_0xbfd5000000000000"
1 } } */
+
+TEST_V4I64 (0x4026000000000000)
+/* { dg-final { scan-assembler-times
"test_V4I64_0x4026000000000000:.*\txvldi\t\\\$xr\[0-9\]+,-986.*-test_V4I64_0x4026000000000000"
1 } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
index 1c9f384e39e..7ad8f45d840 100644
--- a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
@@ -713,10 +713,10 @@
/* { dg-final { scan-assembler-times
"lsx_vfcmp_sune_d:.*vfcmp\\.sune\\.d.*lsx_vfcmp_sune_d" 1 } } */
/* { dg-final { scan-assembler-times
"lsx_vfcmp_sune_s:.*vfcmp\\.sune\\.s.*lsx_vfcmp_sune_s" 1 } } */
/* { dg-final { scan-assembler-times
"lsx_vfcmp_sun_s:.*vfcmp\\.sun\\.s.*lsx_vfcmp_sun_s" 1 } } */
-/* { dg-final { scan-assembler-times "lsx_vrepli_b:.*vrepli\\.b.*lsx_vrepli_b"
1 } } */
-/* { dg-final { scan-assembler-times "lsx_vrepli_d:.*vrepli\\.d.*lsx_vrepli_d"
1 } } */
-/* { dg-final { scan-assembler-times "lsx_vrepli_h:.*vrepli\\.h.*lsx_vrepli_h"
1 } } */
-/* { dg-final { scan-assembler-times "lsx_vrepli_w:.*vrepli\\.w.*lsx_vrepli_w"
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vrepli_b:.*vldi.*lsx_vrepli_b" 1 } }
*/
+/* { dg-final { scan-assembler-times "lsx_vrepli_d:.*vldi.*lsx_vrepli_d" 1 } }
*/
+/* { dg-final { scan-assembler-times "lsx_vrepli_h:.*vldi.*lsx_vrepli_h" 1 } }
*/
+/* { dg-final { scan-assembler-times "lsx_vrepli_w:.*vldi.*lsx_vrepli_w" 1 } }
*/
typedef signed char v16i8 __attribute__ ((vector_size (16), aligned (16)));
typedef signed char v16i8_b __attribute__ ((vector_size (16), aligned (1)));
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vldi-2.c
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vldi-2.c
new file mode 100644
index 00000000000..a756f96dda4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vldi-2.c
@@ -0,0 +1,93 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlasx" } */
+
+#include <lsxintrin.h>
+
+#define TEST_V8I16(imm) \
+void \
+test_v8i16_##imm (v8i16 *vec) \
+ { \
+ v8i16 temp = {imm, imm, imm, imm, \
+ imm, imm, imm, imm}; \
+ *vec = temp; \
+ }
+
+#define TEST_V4I32(imm) \
+void \
+test_v4i32_##imm (v4i32 *vec) \
+ { \
+ v4i32 temp = {imm, imm, imm, imm}; \
+ *vec = temp; \
+ }
+
+#define TEST_V4I32_2(imm1, imm2) \
+void \
+test_v4i32_2_##imm1 (v4i32 *vec) \
+ { \
+ v4i32 temp = {imm1, imm2, imm1, imm2};\
+ *vec = temp; \
+ }
+
+#define TEST_V2I64(imm) \
+void \
+test_v2i64_##imm (v2i64 *vec) \
+ { \
+ v2i64 temp = {imm, imm}; \
+ *vec = temp; \
+ }
+
+/* 4'b0001:data={2{16'b0,x[7:0],8'b0}}. */
+TEST_V4I32 (0x3a00)
+/* { dg-final { scan-assembler-times
"test_v4i32_0x3a00:.*\tvldi\t\\\$vr\[0-9\]+,-3782.*-test_v4i32_0x3a00" 1 } } */
+
+/* 4'b0010:data={2{8'b0,x[7:0],16'b0}}. */
+TEST_V4I32 (0x3a0000)
+/* { dg-final { scan-assembler-times
"test_v4i32_0x3a0000:.*\tvldi\t\\\$vr\[0-9\]+,-3526.*-test_v4i32_0x3a0000" 1 }
} */
+
+/* 4'b0011:data={2{x[7:0],24'b0}}. */
+TEST_V4I32 (0x3a000000)
+/* { dg-final { scan-assembler-times
"test_v4i32_0x3a000000:.*\tvldi\t\\\$vr\[0-9\]+,-3270.*-test_v4i32_0x3a000000"
1 } } */
+
+/* 4'b0101:data={4{x[7:0],8'b0}}. */
+TEST_V8I16 (0x3a00)
+/* { dg-final { scan-assembler-times
"test_v8i16_0x3a00:.*\tvldi\t\\\$vr\[0-9\]+,-2758.*-test_v8i16_0x3a00" 1 } } */
+
+/* 4'b0110:data={2{16'b0,x[7:0],8'hFF}}. */
+TEST_V4I32 (0x3aff)
+/* { dg-final { scan-assembler-times
"test_v4i32_0x3aff:.*\tvldi\t\\\$vr\[0-9\]+,-2502.*-test_v4i32_0x3aff" 1 } } */
+
+/* 4'b0111:data={2{8'b0,x[7:0],16'hFFFF}}. */
+TEST_V4I32 (0x3affff)
+/* { dg-final { scan-assembler-times
"test_v4i32_0x3affff:.*\tvldi\t\\\$vr\[0-9\]+,-2246.*-test_v4i32_0x3affff" 1 }
} */
+
+/* 4'b1001:data={{8{x[7]}},{8{x[6]}},{8{x[5]}},{8{x[4]}},{8{x[3]}},{8{x[2]}},
+ * {8{x[1]}},{8{x[0]}}}. */
+TEST_V2I64 (0xffffff0000ffff00)
+/* { dg-final { scan-assembler-times
"test_v2i64_0xffffff0000ffff00:.*\tvldi\t\\\$vr\[0-9\]+,-1562.*-test_v2i64_0xffffff0000ffff00"
1 } } */
+
+TEST_V2I64 (0xffff0000ff)
+/* { dg-final { scan-assembler-times
"test_v2i64_0xffff0000ff:.*\tvldi\t\\\$vr\[0-9\]+,-1767.*-test_v2i64_0xffff0000ff"
1 } } */
+
+TEST_V4I32_2 (0xffffff00, 0);
+/* { dg-final { scan-assembler-times
"test_v4i32_2_0xffffff00:.*\tvldi\t\\\$vr\[0-9\]+,-1778.*-test_v4i32_2_0xffffff00"
1 } } */
+
+/* 4'b1010:data={2{x[7],~x[6],{5{x[6]}},x[5:0],19'b0}}. */
+TEST_V4I32 (0xbf180000)
+/* { dg-final { scan-assembler-times
"test_v4i32_0xbf180000:.*\tvldi\t\\\$vr\[0-9\]+,-1309.*-test_v4i32_0xbf180000"
1 } } */
+
+TEST_V4I32 (0x41e00000)
+/* { dg-final { scan-assembler-times
"test_v4i32_0x41e00000:.*\tvldi\t\\\$vr\[0-9\]+,-1476.*-test_v4i32_0x41e00000"
1 } } */
+
+/* 4'b1011:data={32'b0,x[7],~x[6],{5{x[6]}},x[5:0],19'b0}. */
+TEST_V2I64 (0xbe180000)
+/* { dg-final { scan-assembler-times
"test_v2i64_0xbe180000:.*\tvldi\t\\\$vr\[0-9\]+,-1085.*-test_v2i64_0xbe180000"
1 } } */
+
+TEST_V2I64 (0x41e00000)
+/* { dg-final { scan-assembler-times
"test_v2i64_0x41e00000:.*\tvldi\t\\\$vr\[0-9\]+,-1220.*-test_v2i64_0x41e00000"
1 } } */
+
+/* 4'b1100:data={x[7],~x[6],{8{x[6]}},x[5:0],48'b0}. */
+TEST_V2I64 (0xbfd5000000000000)
+/* { dg-final { scan-assembler-times
"test_v2i64_0xbfd5000000000000:.*\tvldi\t\\\$vr\[0-9\]+,-811.*-test_v2i64_0xbfd5000000000000"
1 } } */
+
+TEST_V2I64 (0x4026000000000000)
+/* { dg-final { scan-assembler-times
"test_v2i64_0x4026000000000000:.*\tvldi\t\\\$vr\[0-9\]+,-986.*-test_v2i64_0x4026000000000000"
1 } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/vrepli.c
b/gcc/testsuite/gcc.target/loongarch/vrepli.c
index 8deeb478890..8eef4890f61 100644
--- a/gcc/testsuite/gcc.target/loongarch/vrepli.c
+++ b/gcc/testsuite/gcc.target/loongarch/vrepli.c
@@ -1,7 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mlasx" } */
-/* { dg-final { scan-assembler "\tvrepli\\.b\t\\\$vr\[0-9\]+,-35" } } */
-/* { dg-final { scan-assembler "\txvrepli\\.b\t\\\$xr\[0-9\]+,-35" } } */
+/* { dg-final { scan-assembler "\tvldi\t\\\$vr\[0-9\]+,221" } } */
+/* { dg-final { scan-assembler "\txvldi\t\\\$xr\[0-9\]+,221" } } */
int f __attribute__((vector_size (16)));
int g __attribute__((vector_size (32)));
--
2.34.1
