On 06/11/2025 09:31, Andre Vieira wrote:
This patch fixes the CMSE register clearing to make sure we don't clear
registers used by a function call. Before this patch the algorithm would only
correctly handle registers with padding bits to clear, any registers that were
fully utilised would be wrongfully cleared.
gcc/ChangeLog:
PR target/122539
* config/arm/arm.cc (comp_not_to_clear_mask_str_un): Update
not_to_clear_reg_mask for union members.
gcc/testsuite/ChangeLog:
* gcc.target/arm/cmse/union-3.x: New test.
* gcc.target/arm/cmse/baseline/union-3.c: New test.
* gcc.target/arm/cmse/mainline/8m/union-3.c: New test.
* gcc.target/arm/cmse/mainline/8_1m/union-3.c: New test.
---
gcc/config/arm/arm.cc | 3 ++
.../gcc.target/arm/cmse/baseline/union-3.c | 29 ++++++++++++++++
.../arm/cmse/mainline/8_1m/union-3.c | 32 ++++++++++++++++++
.../gcc.target/arm/cmse/mainline/8m/union-3.c | 33 +++++++++++++++++++
gcc/testsuite/gcc.target/arm/cmse/union-3.x | 23 +++++++++++++
5 files changed, 120 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/arm/cmse/baseline/union-3.c
create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8_1m/union-3.c
create mode 100644 gcc/testsuite/gcc.target/arm/cmse/mainline/8m/union-3.c
create mode 100644 gcc/testsuite/gcc.target/arm/cmse/union-3.x
OK.
As an aside:
+** lsrs r3, r3, #1
+** lsls r3, r3, #1
On mainline profile cores, this can be done more efficiently with
bic r3, r3, #1
Same code size, but more efficient for the CPU.
R.
