On 10/29/25 8:04 PM, Kuan-Lin Chen wrote:
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Add andes-25-series.
(RISCV_CORE): Add Andes 25-series cpu list.
* config/riscv/riscv-opts.h
(enum riscv_microarchitecture_type): Add andes_vicuna.
* config/riscv/riscv.cc: Add andes_vicuna_tune_info.
* config/riscv/riscv.md: Add andes_vicuna.
* doc/riscv-mcpu.texi: Regenerated for Andes cpu list.
* doc/riscv-mtune.texi: Regenerated for andes-25-series.
* config/riscv/andes-vicuna.md: New file.
---
+ false, /* use_divmod_expansion */
I strongly suspect this should be "true".
+ true, /* use_zero_stride_load
*/
And this likely should be "false".
Kito's comments about naming still apply. With those changes this will
be OK. If you strongly disagree on the divmod and zero-stride-load
leave them as-is.
Jeff
