Trivial improvement for 32 bit rotates on rv64 that I noticed while
looking at a PR121778. We were failing to use the _extended variant
when the rotation count was a constant on rv64 after cobbling together a
prototype match.pd pattern.
I suspect the guard was added by Jivan to avoid having to muck around in
the thead bitmanip extensions. But that's a bit of speculation on my part.
I reviewed the thead extensions and they do the expected thing for the W
form rotate. So this patch adds a pattern to thead.md that exposes the
sign extension and removes the restriction on generating that form from
bitmanip.md.
I can envision this will help something, somewhere, but it's generally
going to be very much on the margins. I didn't take the time to
find/construct a testcase showing the missed optimization. There is one
test that triggers the thead W form rotate (xtheadbb-srri.c), so that's
got some coverage and passes (and I verified it's using the version with
the sign extension exposed, so that's good). PR121778 will trigger the
missed optimization if we add a suitable match.pd.
Regression tested on riscv32-elf and riscv64-elf. Bootstraps on the BPI
and Pioneer are in flight, but won't be finished for a long time.
Obviously waiting on pre-commit CI before moving forward.
jeff
* config/riscv/bitmanip.md (rotrsi3): Use the sign extended form
for 32 bit rotates on TARGET_64BIT, even for constant counts.
* config/riscv/xthead.md (th_srrisi3_extended): New pattern.
(th_srri<mode>3): Adjust formatting.
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 697198fcc913..166ddd9db9e6 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -357,7 +357,7 @@ (define_expand "rotrsi3"
{
if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode))
FAIL;
- if (TARGET_64BIT && register_operand (operands[2], QImode))
+ if (TARGET_64BIT)
{
rtx t = gen_reg_rtx (DImode);
emit_insn (gen_rotrsi3_sext (t, operands[1], operands[2]));
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 20e82e68df2a..97b81760922f 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -34,7 +34,7 @@ (define_insn "*th_addsl<mode>4"
(define_insn "*th_srri<mode>3"
[(set (match_operand:GPR 0 "register_operand" "=r")
(rotatert:GPR (match_operand:GPR 1 "register_operand" "r")
- (match_operand 2 "const_int_operand" "n")))]
+ (match_operand 2 "const_int_operand" "n")))]
"TARGET_XTHEADBB && (TARGET_64BIT || <MODE>mode == SImode)"
{
bool wform = TARGET_64BIT && (<MODE>mode == SImode);
@@ -45,6 +45,22 @@ (define_insn "*th_srri<mode>3"
[(set_attr "type" "bitmanip")
(set_attr "mode" "<GPR:MODE>")])
+;; Version with explicit sign extension to facilitate sign extension
+;; removal.
+(define_insn "*th_srrisi3_extended"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extend:DI
+ (rotatert:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand 2 "const_int_operand" "n"))))]
+ "TARGET_XTHEADBB && TARGET_64BIT"
+ {
+ operands[2] = GEN_INT (INTVAL (operands[2])
+ & (GET_MODE_BITSIZE (SImode) - 1));
+ return "th.srriw\t%0,%1,%2";
+ }
+ [(set_attr "type" "bitmanip")
+ (set_attr "mode" "SI")])
+
(define_insn "*th_ext<mode>4"
[(set (match_operand:GPR 0 "register_operand" "=r")
(sign_extract:GPR (match_operand:GPR 1 "register_operand" "r")
