Re: [pushed][PATCH] LoongArch: Only allow valid binary op when optimize conditional move

[Lulu Cheng]

Pushed to r15-10467.

在 2025/10/30 上午11:30, Lulu Cheng 写道:

Pushed to r16-4722.

在 2025/10/29 下午4:07, Jinyang He 写道:

It is wrong that optimize from `if (cond) dest op= 1 << shift` to
`dest op= (cond ? 1 : 0) << shift` when `dest op 0 != dest`.
Like `and`, `mul` or `div`.
And in this optimization `mul` and `div` is optimized to shift.

gcc/ChangeLog:

    * config/loongarch/loongarch.cc
    (loongarch_expand_conditional_move): Only allow valid binary
    op when optimize conditional move.

gcc/testsuite/ChangeLog:

    * gcc.target/loongarch/conditional-move-opt-1.c: Remove mul.
    * gcc.target/loongarch/conditional-move-opt-2.c: Remove and.
    * gcc.target/loongarch/conditional-move-opt-3.c: New test.

Co-Authored-By: Peng Fan <fanp...@loongson.cn>
---
  gcc/config/loongarch/loongarch.cc             | 26 ++++++++++++++++---
  .../loongarch/conditional-move-opt-1.c        |  4 +--
  .../loongarch/conditional-move-opt-2.c        |  2 +-
  .../loongarch/conditional-move-opt-3.c        | 14 ++++++++++
  4 files changed, 40 insertions(+), 6 deletions(-)

  create mode 100644 gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc

index 5c2a9ebbe20..a2a920fdd88 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc

@@ -5490,12 +5490,32 @@ loongarch_expand_conditional_move (rtx *operands)

          }
      }
  +      auto is_binary_op_0_keep_orig = [](enum rtx_code code)
+    {
+      switch (code)
+        {
+        case PLUS:
+        case MINUS:
+        case IOR:
+        case XOR:
+        case ROTATE:
+        case ROTATERT:
+        case ASHIFT:
+        case ASHIFTRT:
+        case LSHIFTRT:
+          return true;
+        default:
+          return false;
+        }
+    };
+
        /* Check if the optimization conditions are met.  */
        if (value_if_true_insn
        && value_if_false_insn
-      /* Make sure that value_if_false and var are the same. */
-      && BINARY_P (value_if_true_insn_src
-               = SET_SRC (single_set (value_if_true_insn)))
+      /* Make sure that the orig value OP 0 keep orig.  */
+      && (value_if_true_insn_src
+          = SET_SRC (single_set (value_if_true_insn)))
+      && is_binary_op_0_keep_orig ( GET_CODE (value_if_true_insn_src))
        /* Make sure that both value_if_true and value_if_false
           has the same var.  */
        && rtx_equal_p (XEXP (value_if_true_insn_src, 0),

diff --git a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c

index ed13471aa90..47802aa9688 100644
--- a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c
+++ b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c
@@ -27,7 +27,7 @@ void
  test_lt ()
  {
    if (lm < ln)
-    lr *= (1 << 16);
+    lr += (1 << 16);
    lr += lm;
  }
  @@ -35,7 +35,7 @@ void
  test_le ()
  {
    if (lm <= ln)
-    lr = lm * ((long)1 << 32);
+    lr = lm + ((long)1 << 32);
    else
      lr = lm;
    lr += lm;

diff --git a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c

index ac72d4d933a..743fd5e670e 100644
--- a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c
+++ b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c
@@ -29,7 +29,7 @@ void
  test_lez ()
  {
    if (lm <= 0)
-    lr &= (1 << 16);
+    lr |= (1 << 16);
    lr += lm;
  }

  diff --git a/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c

new file mode 100644
index 00000000000..95887980cc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/conditional-move-opt-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "maskeqz" } } */
+/* { dg-final { scan-assembler "masknez" } } */
+
+extern long lm, ln, lr;
+
+void
+test_and ()
+{
+  if (lm < 0)
+    lr &= (1 << 16);
+  lr += lm;
+}