From: Christophe Lyon <[email protected]>
The original versions of these tests only took into account code
generated with -mfloat-abi=hard.
Depending on how the toolchain is configured, arm_v8_1m_mve may use
-mfloat-abi-softfp, which generates a different instructions order.
Depending on the -mtune setting, the order can also vary, so the patch
adds -fno-schedule-insns -fno-schedule-insns2 to avoid such
maintenance issues.
In particular, this fixes the failures with:
-mthumb -march=armv7e-m+fp.dp -mtune=cortex-m7 -mfloat-abi=hard -mfpu=auto
-mthumb -march=armv6s-m -mtune=cortex-m0 -mfloat-abi=soft -mfpu=auto
gcc/testsuite/ChangeLog:
PR target/122189
* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
---
.../gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 10 +++++-----
.../gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 10 +++++-----
.../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 10 +++++-----
.../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 10 +++++-----
4 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
index c5a58782cdef..1802c20a3971 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
@@ -1,6 +1,6 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
+/* { dg-additional-options "-O2 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
@@ -14,12 +14,12 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** vpst(?: @.*|)
** ...
** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
@@ -41,12 +41,12 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** vpst(?: @.*|)
** ...
** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
index 23908a4273db..64f221df8682 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
@@ -1,6 +1,6 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
+/* { dg-additional-options "-O2 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
@@ -14,12 +14,12 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** vpst(?: @.*|)
** ...
** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
@@ -41,12 +41,12 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** vpst(?: @.*|)
** ...
** vadct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
index 940e2edfcc5e..da36d694ddfb 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
@@ -1,6 +1,6 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
+/* { dg-additional-options "-O2 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
@@ -14,12 +14,12 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** vpst(?: @.*|)
** ...
** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
@@ -41,12 +41,12 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** vpst(?: @.*|)
** ...
** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
index 478b938f8f74..555690f5fb80 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
@@ -1,6 +1,6 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
-/* { dg-additional-options "-O2" } */
+/* { dg-additional-options "-O2 -fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
@@ -14,12 +14,12 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** vpst(?: @.*|)
** ...
** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
@@ -41,12 +41,12 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
-** ...
** bfi (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
** vmsr FPSCR_nzcvqc, (?:ip|fp|r[0-9]+)(?: @.*|)
** ...
+** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
+** ...
** vpst(?: @.*|)
** ...
** vsbct.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|)
