This patch fixes many, though not all, of the aarch64-specific duplicate
testnames.
Similarly to the arm port, most of these are a mix of duplicate scan-assembler
tests
that have been addressed by converting the code to use check-function-bodies, or
outright bugs in the test.
There are a couple of files that still contain duplicates
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/asm-flag-1.c: Scan for lt.
* gcc.target/aarch64/vector-compare-5.c: Use scan-tree-dump-times.
* gcc.target/aarch64/simd/fold_to_highpart_5.c: Scan for sabal2 and
uabal2.
* gcc.target/aarch64/sve/mixed_size_6.c: Scan for absense of index with
2.
* gcc.target/aarch64/declare-simd-2.c: Remove duplicate scan-assembler
patterns.
* gcc.target/aarch64/sve/arith_1.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_1.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_5.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_1.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_5.c: Likewise
* gcc.target/aarch64/sve/pcs/annotate_1.c: Likewise.
* gcc.target/aarch64/sve/uzp1_1.c: Likewise.
* gcc.target/aarch64/sve/uzp2_1.c: Likewise.
* gcc.target/aarch64/scalar_intrinsics.c: Scan for ursra.
* gcc.target/aarch64/singleton_intrinsics_1.c: Likewise.
* gcc.target/aarch64/sve/cond_fmaxnm_3.c: Fix register modifiers in
scan patterns.
* gcc.target/aarch64/sve/cond_fmaxnm_7.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_3.c: Likewise.
* gcc.target/aarch64/sve/cond_fminnm_7.c: Likewise.
* gcc.target/aarch64/sve/cond_fmul_3.c: Likewise.
* gcc.target/aarch64/sve/cond_fsubr_3.c: Likewise.
* gcc.target/aarch64/ldp_stp_18.c: Fix typos in scan patterns.
* gcc.target/aarch64/sve/pcs/return_6.c: Likewise.
* gcc.target/aarch64/ror_2.c: Adjust constants to ensure scan-assembler
patterns
are unique.
* gcc.target/aarch64/sve/struct_move_3.c: Likewise.
* gcc.target/aarch64/sve/struct_move_6.c: Likewise.
* gcc.target/aarch64/builtin_pld_pli.c: Use check-function-bodies
* gcc.target/aarch64/csinc-1.c: Likewise.
* gcc.target/aarch64/csneg-1.c: Likewise.
* gcc.target/aarch64/flt_mov_immediate_1.c: Likewise.
* gcc.target/aarch64/scalar_shift_1.c: Likewise.
---
gcc/testsuite/gcc.target/aarch64/asm-flag-1.c | 2 +-
.../gcc.target/aarch64/builtin_pld_pli.c | 72 ++++++-----
gcc/testsuite/gcc.target/aarch64/csinc-1.c | 43 ++++++-
gcc/testsuite/gcc.target/aarch64/csneg-1.c | 44 +++++--
.../gcc.target/aarch64/declare-simd-2.c | 3 -
.../gcc.target/aarch64/flt_mov_immediate_1.c | 50 +++++---
gcc/testsuite/gcc.target/aarch64/ldp_stp_18.c | 4 +-
gcc/testsuite/gcc.target/aarch64/ror_2.c | 12 +-
.../gcc.target/aarch64/scalar_intrinsics.c | 2 +-
.../gcc.target/aarch64/scalar_shift_1.c | 114 +++++++++++++-----
.../aarch64/simd/fold_to_highpart_5.c | 4 +-
.../aarch64/singleton_intrinsics_1.c | 2 +-
.../gcc.target/aarch64/sve/arith_1.c | 2 +-
.../gcc.target/aarch64/sve/cond_fmaxnm_1.c | 4 -
.../gcc.target/aarch64/sve/cond_fmaxnm_3.c | 4 +-
.../gcc.target/aarch64/sve/cond_fmaxnm_5.c | 4 -
.../gcc.target/aarch64/sve/cond_fmaxnm_7.c | 4 +-
.../gcc.target/aarch64/sve/cond_fminnm_1.c | 4 -
.../gcc.target/aarch64/sve/cond_fminnm_3.c | 4 +-
.../gcc.target/aarch64/sve/cond_fminnm_5.c | 4 -
.../gcc.target/aarch64/sve/cond_fminnm_7.c | 4 +-
.../gcc.target/aarch64/sve/cond_fmul_3.c | 4 +-
.../gcc.target/aarch64/sve/cond_fsubr_3.c | 4 +-
.../gcc.target/aarch64/sve/mixed_size_6.c | 4 +-
.../gcc.target/aarch64/sve/pcs/annotate_1.c | 1 -
.../gcc.target/aarch64/sve/pcs/return_6.c | 2 +-
.../gcc.target/aarch64/sve/struct_move_3.c | 12 +-
.../gcc.target/aarch64/sve/struct_move_6.c | 12 +-
gcc/testsuite/gcc.target/aarch64/sve/uzp1_1.c | 3 -
gcc/testsuite/gcc.target/aarch64/sve/uzp2_1.c | 3 -
.../gcc.target/aarch64/vector-compare-5.c | 10 +-
31 files changed, 280 insertions(+), 161 deletions(-)
diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c
b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c
index 49901e59c38..7b07cdd7721 100644
--- a/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c
@@ -30,6 +30,6 @@ void f(char *out)
/* { dg-final { scan-assembler "cset.*, hi" } } */
/* { dg-final { scan-assembler "cset.*, ls" } } */
/* { dg-final { scan-assembler "cset.*, ge" } } */
-/* { dg-final { scan-assembler "cset.*, ls" } } */
+/* { dg-final { scan-assembler "cset.*, lt" } } */
/* { dg-final { scan-assembler "cset.*, gt" } } */
/* { dg-final { scan-assembler "cset.*, le" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/builtin_pld_pli.c
b/gcc/testsuite/gcc.target/aarch64/builtin_pld_pli.c
index 8cbaa97c00c..0e60baf057b 100644
--- a/gcc/testsuite/gcc.target/aarch64/builtin_pld_pli.c
+++ b/gcc/testsuite/gcc.target/aarch64/builtin_pld_pli.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-march=armv8-a -O2" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
#include <arm_acle.h>
@@ -38,23 +39,27 @@ prefetch_for_read_write (void *a)
__pldx (PST, SLC, KEEP, a);
__pldx (PST, SLC, STRM, a);
}
-
-/* { dg-final { scan-assembler "prfm\tPLDL1KEEP, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLDL1STRM, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLDL2KEEP, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLDL2STRM, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLDL3KEEP, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLDL3STRM, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLDSLCKEEP, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLDSLCSTRM, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPSTL1KEEP, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPSTL1STRM, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPSTL2KEEP, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPSTL2STRM, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPSTL3KEEP, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPSTL3STRM, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPSTSLCKEEP, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPSTSLCSTRM, \\\[x\[0-9\]+\\\]" } } */
+/*
+** prefetch_for_read_write:
+** ...
+** prfm\tPLDL1KEEP, \[x[0-9]+\]
+** prfm\tPLDL1STRM, \[x[0-9]+\]
+** prfm\tPLDL2KEEP, \[x[0-9]+\]
+** prfm\tPLDL2STRM, \[x[0-9]+\]
+** prfm\tPLDL3KEEP, \[x[0-9]+\]
+** prfm\tPLDL3STRM, \[x[0-9]+\]
+** prfm\tPLDSLCKEEP, \[x[0-9]+\]
+** prfm\tPLDSLCSTRM, \[x[0-9]+\]
+** prfm\tPSTL1KEEP, \[x[0-9]+\]
+** prfm\tPSTL1STRM, \[x[0-9]+\]
+** prfm\tPSTL2KEEP, \[x[0-9]+\]
+** prfm\tPSTL2STRM, \[x[0-9]+\]
+** prfm\tPSTL3KEEP, \[x[0-9]+\]
+** prfm\tPSTL3STRM, \[x[0-9]+\]
+** prfm\tPSTSLCKEEP, \[x[0-9]+\]
+** prfm\tPSTSLCSTRM, \[x[0-9]+\]
+** ...
+*/
void
prefetch_simple (void *a)
@@ -62,9 +67,13 @@ prefetch_simple (void *a)
__pld (a);
__pli (a);
}
-
-/* { dg-final { scan-assembler "prfm\tPLDL1KEEP, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLIL1KEEP, \\\[x\[0-9\]+\\\]" } } */
+/*
+** prefetch_simple:
+** ...
+** prfm\tPLDL1KEEP, \[x[0-9]+\]
+** prfm\tPLIL1KEEP, \[x[0-9]+\]
+** ...
+*/
void
prefetch_instructions (void *a)
@@ -78,13 +87,16 @@ prefetch_instructions (void *a)
__plix (SLC, KEEP, a);
__plix (SLC, STRM, a);
}
-
-/* { dg-final { scan-assembler "prfm\tPLIL1KEEP, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLIL1STRM, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLIL2KEEP, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLIL2STRM, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLIL3KEEP, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLIL3STRM, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLISLCKEEP, \\\[x\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "prfm\tPLISLCSTRM, \\\[x\[0-9\]+\\\]" } } */
-
+/*
+** prefetch_instructions:
+** ...
+** prfm\tPLIL1KEEP, \[x[0-9]+\]
+** prfm\tPLIL1STRM, \[x[0-9]+\]
+** prfm\tPLIL2KEEP, \[x[0-9]+\]
+** prfm\tPLIL2STRM, \[x[0-9]+\]
+** prfm\tPLIL3KEEP, \[x[0-9]+\]
+** prfm\tPLIL3STRM, \[x[0-9]+\]
+** prfm\tPLISLCKEEP, \[x[0-9]+\]
+** prfm\tPLISLCSTRM, \[x[0-9]+\]
+** ...
+*/
diff --git a/gcc/testsuite/gcc.target/aarch64/csinc-1.c
b/gcc/testsuite/gcc.target/aarch64/csinc-1.c
index 132a0f67939..53e1ae2c7d9 100644
--- a/gcc/testsuite/gcc.target/aarch64/csinc-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/csinc-1.c
@@ -1,16 +1,22 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
unsigned int
test_csinc32_ifcvt(unsigned int w0,
unsigned int w1,
unsigned int w2) {
- /* { dg-final { scan-assembler "csinc\tw\[0-9\]*.*ne" } } */
if (w0 == w1)
++ w2;
return w2;
}
+/*
+** test_csinc32_ifcvt:
+** cmp\tw0, w1
+** cinc\tw0, w2, eq
+** ret
+*/
unsigned int
test_csinc32_condasn1(unsigned int w0,
@@ -19,10 +25,15 @@ test_csinc32_condasn1(unsigned int w0,
unsigned int w3) {
unsigned int w4;
- /* { dg-final { scan-assembler "csinc\tw\[0-9\]*.*ne" } } */
w4 = (w0 == w1) ? (w3 + 1) : w2;
return w4;
}
+/*
+** test_csinc32_condasn1:
+** cmp\tw0, w1
+** csinc\tw0, w2, w3, ne
+** ret
+*/
unsigned int
test_csinc32_condasn2(unsigned int w0,
@@ -31,21 +42,31 @@ test_csinc32_condasn2(unsigned int w0,
unsigned int w3) {
unsigned int w4;
- /* { dg-final { scan-assembler "csinc\tw\[0-9\]*.*eq" } } */
w4 = (w0 == w1) ? w2 : (w3 + 1);
return w4;
}
+/*
+** test_csinc32_condasn2:
+** cmp\tw0, w1
+** csinc\tw0, w2, w3, eq
+** ret
+*/
unsigned long long
test_csinc64_ifcvt(unsigned long long x0,
unsigned long long x1,
unsigned long long x2) {
- /* { dg-final { scan-assembler "csinc\tx\[0-9\]*.*ne" } } */
if (x0 == x1)
++ x2;
return x2;
}
+/*
+** test_csinc64_ifcvt:
+** cmp\tx0, x1
+** cinc\tx0, x2, eq
+** ret
+*/
unsigned long long
test_csinc64_condasn1(unsigned long long x0,
@@ -54,10 +75,15 @@ test_csinc64_condasn1(unsigned long long x0,
unsigned long long x3) {
unsigned long long x4;
- /* { dg-final { scan-assembler "csinc\tx\[0-9\]*.*ne" } } */
x4 = (x0 == x1) ? (x3 + 1) : x2;
return x4;
}
+/*
+** test_csinc64_condasn1:
+** cmp\tx0, x1
+** csinc\tx0, x2, x3, ne
+** ret
+*/
unsigned long long
test_csinc64_condasn2(unsigned long long x0,
@@ -66,7 +92,12 @@ test_csinc64_condasn2(unsigned long long x0,
unsigned long long x3) {
unsigned long long x4;
- /* { dg-final { scan-assembler "csinc\tx\[0-9\]*.*eq" } } */
x4 = (x0 == x1) ? x2 : (x3 + 1);
return x4;
}
+/*
+** test_csinc64_condasn2:
+** cmp\tx0, x1
+** csinc\tx0, x2, x3, eq
+** ret
+*/
diff --git a/gcc/testsuite/gcc.target/aarch64/csneg-1.c
b/gcc/testsuite/gcc.target/aarch64/csneg-1.c
index 4860d64c935..2533e7b56fe 100644
--- a/gcc/testsuite/gcc.target/aarch64/csneg-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/csneg-1.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
int
test_csneg32_condasn1(int w0,
@@ -8,10 +9,15 @@ test_csneg32_condasn1(int w0,
int w3) {
int w4;
- /* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*ne" } } */
w4 = (w0 == w1) ? -w3 : w2;
return w4;
}
+/*
+** test_csneg32_condasn1:
+** cmp\tw0, w1
+** csneg\tw0, w2, w3, ne
+** ret
+*/
int
test_csneg32_condasn2(int w0,
@@ -20,10 +26,15 @@ test_csneg32_condasn2(int w0,
int w3) {
int w4;
- /* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*eq" } } */
w4 = (w0 == w1) ? w3 : -w2;
return w4;
}
+/*
+** test_csneg32_condasn2:
+** cmp\tw0, w1
+** csneg\tw0, w3, w2, eq
+** ret
+*/
long long
test_csneg64_condasn1(long long x0,
@@ -32,10 +43,15 @@ test_csneg64_condasn1(long long x0,
long long x3) {
long long x4;
- /* { dg-final { scan-assembler "csneg\tx\[0-9\]*.*ne" } } */
x4 = (x0 == x1) ? -x3 : x2;
return x4;
}
+/*
+** test_csneg64_condasn1:
+** cmp\tx0, x1
+** csneg\tx0, x2, x3, ne
+** ret
+*/
long long
test_csneg64_condasn2(long long x0,
@@ -44,27 +60,41 @@ test_csneg64_condasn2(long long x0,
long long x3) {
long long x4;
- /* { dg-final { scan-assembler "csneg\tx\[0-9\]*.*eq" } } */
x4 = (x0 == x1) ? x3 : -x2;
return x4;
}
+/*
+** test_csneg64_condasn2:
+** cmp\tx0, x1
+** csneg\tx0, x3, x2, eq
+** ret
+*/
int test_csneg_cmp(int x)
{
- /* { dg-final { scan-assembler "csneg\tw\[0-9\]" } } */
if (x > 3)
x = -x;
return x;
}
+/*
+** test_csneg_cmp:
+** cmp\tw0, 3
+** csneg\tw0, w0, w0, le
+** ret
+*/
unsigned long long
test_csneg_uxtw (unsigned int a,
unsigned int b,
unsigned int c)
{
- /* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*ne" } } */
- /* { dg-final { scan-assembler-not "uxtw\tw\[0-9\]*.*" } } */
unsigned int val;
val = a ? b: -c;
return val;
}
+/*
+** test_csneg_uxtw:
+** cmp\tw0, 0
+** csneg\tw0, w1, w2, ne
+** ret
+*/
diff --git a/gcc/testsuite/gcc.target/aarch64/declare-simd-2.c
b/gcc/testsuite/gcc.target/aarch64/declare-simd-2.c
index 2f4d3a866e5..f8ef997db08 100644
--- a/gcc/testsuite/gcc.target/aarch64/declare-simd-2.c
+++ b/gcc/testsuite/gcc.target/aarch64/declare-simd-2.c
@@ -52,10 +52,7 @@ void f05 (short a, short *b, short c)
}
/* { dg-final { scan-assembler {_ZGVnN4ul2v_f05:} } } */
-/* { dg-final { scan-assembler {_ZGVnN4ul2v_f05:} } } */
-/* { dg-final { scan-assembler {_ZGVnM8ul2v_f05:} } } */
/* { dg-final { scan-assembler {_ZGVnM8ul2v_f05:} } } */
#ifdef __cplusplus
}
#endif
-
diff --git a/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c
b/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c
index 7b92a5ae40f..36a1e345204 100644
--- a/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c
@@ -1,52 +1,74 @@
/* { dg-do compile } */
/* { dg-options "-O3" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
float f0(void)
{
float x = 0.0f;
return x;
}
+/*
+** f0:
+** movi\tv0.2s, #?0
+** ret
+*/
float fn1(void)
{
float x = -0.0f;
return x;
}
+/*
+** fn1:
+** movi\tv0.2s, 0x80, lsl 24
+** ret
+*/
float f1(void)
{
float x = 256.0f;
return x;
}
+/*
+** f1:
+** mov\t(w[0-9]+), 1132462080
+** fmov\ts0, \1
+** ret
+*/
float f2(void)
{
float x = 123256.0f;
return x;
}
+/*
+** f2:
+** mov\t(w[0-9]+), 48128
+** movk\t\1, 0x47f0, lsl 16
+** fmov\ts0, \1
+** ret
+*/
float f3(void)
{
float x = 2.0f;
return x;
}
+/*
+** f3:
+** fmov\ts0, 2\.0e\+0
+** ret
+*/
float f4(void)
{
float x = -20000.1;
return x;
}
-
-
-/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, ?#0" 1
} } */
-/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x80, lsl 24" 1
} } */
-/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x80, lsl 24" 1
} } */
-
-/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 48128" 1
} } */
-/* { dg-final { scan-assembler-times "movk\tw\[0-9\]+, 0x47f0, lsl 16" 1
} } */
-
-/* { dg-final { scan-assembler-times "fmov\ts\[0-9\]+, 2\\\.0e\\\+0" 1 } } */
-
-/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 16435" 1
} } */
-/* { dg-final { scan-assembler-times "movk\tw\[0-9\]+, 0xc69c, lsl 16" 1
} } */
-
+/*
+** f4:
+** mov\t(w[0-9]+), 16435
+** movk\t\1, 0xc69c, lsl 16
+** fmov\ts0, \1
+** ret
+*/
diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_18.c
b/gcc/testsuite/gcc.target/aarch64/ldp_stp_18.c
index ea9fffc2208..49aa0b20ab7 100644
--- a/gcc/testsuite/gcc.target/aarch64/ldp_stp_18.c
+++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_18.c
@@ -107,7 +107,7 @@ CONS4_FN (1, double);
CONS4_FN (2, double);
/*
-** cons2_8_double:
+** cons4_4_double:
** ...
** stp q[0-9]+, .*
** ret
@@ -115,7 +115,7 @@ CONS4_FN (2, double);
CONS4_FN (4, double);
/*
-** cons2_8_double:
+** cons4_8_double:
** ...
** stp q[0-9]+, .*
** ret
diff --git a/gcc/testsuite/gcc.target/aarch64/ror_2.c
b/gcc/testsuite/gcc.target/aarch64/ror_2.c
index 796c1222230..fbea839454a 100644
--- a/gcc/testsuite/gcc.target/aarch64/ror_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/ror_2.c
@@ -175,8 +175,8 @@ tst2 (unsigned x, unsigned y)
int
tst3 (unsigned x, unsigned y)
{
- /* { dg-final { scan-assembler "tst\tw\[0-9\]+, w\[0-9\]+, ror 20\n" } } */
- return ((unsigned long)x & ROR (y, 20)) == 0;
+ /* { dg-final { scan-assembler "tst\tw\[0-9\]+, w\[0-9\]+, ror 21\n" } } */
+ return ((unsigned long)x & ROR (y, 21)) == 0;
}
int
@@ -189,15 +189,15 @@ bics1 (unsigned x, unsigned y)
int
bics2 (unsigned x, unsigned y)
{
- /* { dg-final { scan-assembler "bics\twzr, w\[0-9\]+, w\[0-9\]+, ror 21\n" }
} */
- return (x & ~ROR (y, 21)) == 0;
+ /* { dg-final { scan-assembler "bics\twzr, w\[0-9\]+, w\[0-9\]+, ror 22\n" }
} */
+ return (x & ~ROR (y, 22)) == 0;
}
int
bics3 (unsigned x, unsigned y)
{
- /* { dg-final { scan-assembler "bics\twzr, w\[0-9\]+, w\[0-9\]+, ror 21\n" }
} */
- return (x & (unsigned long)~ROR (y, 21)) == 0;
+ /* { dg-final { scan-assembler "bics\twzr, w\[0-9\]+, w\[0-9\]+, ror 23\n" }
} */
+ return (x & (unsigned long)~ROR (y, 23)) == 0;
}
/* { dg-final { scan-assembler-not "cmp" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
index dcf9dc777ad..094aaff7b1c 100644
--- a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
+++ b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
@@ -913,7 +913,7 @@ test_vrsrad_n_s64 (int64_t a, int64_t b)
return vrsrad_n_s64 (a, b, 3);
}
-/* { dg-final { scan-assembler-times "\\tsrsra\\td\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "\\tursra\\td\[0-9\]+" 1 } } */
uint64_t
test_vrsrad_n_u64 (uint64_t a, uint64_t b)
diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
index 7be1b12a75b..e715f19aa5d 100644
--- a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
/* { dg-options "-O2 -fno-inline -save-temps" } */
-
+/* { dg-final { check-function-bodies "**" "" "" } } */
extern void abort ();
#define force_simd_di(v) asm volatile ("mov %d0, %1.d[0]" :"=w" (v) :"w" (v) :)
@@ -23,8 +23,13 @@ test_lshift_left_sisd_di (UInt64x1 b, UInt64x1 c)
force_simd_di (a);
return a;
}
-/* { dg-final { scan-assembler "shl\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
-/* { dg-final { scan-assembler "ushl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
+/*
+** test_lshift_left_sisd_di:
+** ...
+** shl\t(d[0-9]+), d[0-9]+, 8
+** ushl\td[0-9]+, \1, d[0-9]+
+** ...
+*/
UInt32x1
test_lshift_left_sisd_si (UInt32x1 b, UInt32x1 c)
@@ -38,8 +43,13 @@ test_lshift_left_sisd_si (UInt32x1 b, UInt32x1 c)
force_simd_si (a);
return a;
}
-/* { dg-final { scan-assembler "shl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
-/* "ushl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" (counted later) */
+/*
+** test_lshift_left_sisd_si:
+** ...
+** shl\t(v[0-9]+\.2s), v[0-9]+\.2s, 4
+** ushl\tv[0-9]+\.2s, \1, v[0-9]+\.2s
+** ...
+*/
UInt64x1
test_lshift_right_sisd_di (UInt64x1 b, UInt64x1 c)
@@ -53,9 +63,14 @@ test_lshift_right_sisd_di (UInt64x1 b, UInt64x1 c)
force_simd_di (a);
return a;
}
-/* { dg-final { scan-assembler "ushr\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
-/* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
-/* { dg-final { scan-assembler "ushl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
+/*
+** test_lshift_right_sisd_di:
+** ...
+** ushr\t(d[0-9]+), d[0-9]+, 8
+** neg\t(d[0-9]+), d[0-9]+
+** ushl\td[0-9]+, \1, \2
+** ...
+*/
UInt64x1
test_lshift_right_sisd_si (UInt32x1 b, UInt32x1 c)
@@ -69,9 +84,14 @@ test_lshift_right_sisd_si (UInt32x1 b, UInt32x1 c)
force_simd_si (a);
return a;
}
-/* { dg-final { scan-assembler "ushr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
-/* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
-/* { dg-final { scan-assembler-times "ushl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\
v\[0-9\]+\.2s" 2 } } */
+/*
+** test_lshift_right_sisd_si:
+** ...
+** ushr\t(v[0-9]+\.2s), v[0-9]+\.2s, 4
+** neg\td([0-9]+), d[0-9]+
+** ushl\tv[0-9]+\.2s, \1, v\2\.2s
+** ...
+*/
Int64x1
test_ashift_right_sisd_di (Int64x1 b, Int64x1 c)
@@ -85,9 +105,14 @@ test_ashift_right_sisd_di (Int64x1 b, Int64x1 c)
force_simd_di (a);
return a;
}
-/* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
-/* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
-/* { dg-final { scan-assembler "sshl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
+/*
+** test_ashift_right_sisd_di:
+** ...
+** sshr\t(d[0-9]+), d[0-9]+, 8
+** neg\t(d[0-9]+), d[0-9]+
+** sshl\td[0-9]+, \1, \2
+** ...
+*/
Int32x1
test_ashift_right_sisd_si (Int32x1 b, Int32x1 c)
@@ -101,10 +126,14 @@ test_ashift_right_sisd_si (Int32x1 b, Int32x1 c)
force_simd_si (a);
return a;
}
-/* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
-/* { dg-final { scan-assembler-times "neg\td\[0-9\]+,\ d\[0-9\]+" 4 } } */
-/* { dg-final { scan-assembler "sshl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\
v\[0-9\]+\.2s" } } */
-
+/*
+** test_ashift_right_sisd_si:
+** ...
+** sshr\t(v[0-9]+\.2s), v[0-9]+\.2s, 4
+** neg\td([0-9]+), d[0-9]+
+** sshl\tv[0-9]+\.2s, \1, v\2\.2s
+** ...
+*/
/* The following are to make sure if the integer instructions lsl/lsr/asr are
generated in non-vector scenarios */
@@ -118,8 +147,12 @@ test_lshift_left_int_di (UInt64x1 b, UInt64x1 c)
a = a << c;
return a;
}
-/* { dg-final { scan-assembler "lsl\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
-/* { dg-final { scan-assembler "lsl\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
+/*
+** test_lshift_left_int_di:
+** lsl\t(x[0-9]+), x0, 8
+** lsl\tx0, \1, x1
+** ret
+*/
UInt32x1
test_lshift_left_int_si (UInt32x1 b, UInt32x1 c)
@@ -130,8 +163,12 @@ test_lshift_left_int_si (UInt32x1 b, UInt32x1 c)
a = a << c;
return a;
}
-/* { dg-final { scan-assembler "lsl\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
-/* { dg-final { scan-assembler "lsl\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
+/*
+** test_lshift_left_int_si:
+** lsl\t(w[0-9]+), w0, 4
+** lsl\tw0, \1, w1
+** ret
+*/
UInt64x1
test_lshift_right_int_di (UInt64x1 b, UInt64x1 c)
@@ -142,8 +179,12 @@ test_lshift_right_int_di (UInt64x1 b, UInt64x1 c)
a = a >> c;
return a;
}
-/* { dg-final { scan-assembler "lsr\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
-/* { dg-final { scan-assembler "lsr\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
+/*
+** test_lshift_right_int_di:
+** lsr\t(x[0-9]+), x0, 8
+** lsr\tx0, \1, x1
+** ret
+*/
UInt32x1
test_lshift_right_int_si (UInt32x1 b, UInt32x1 c)
@@ -154,8 +195,12 @@ test_lshift_right_int_si (UInt32x1 b, UInt32x1 c)
a = a >> c;
return a;
}
-/* { dg-final { scan-assembler "lsr\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
-/* { dg-final { scan-assembler "lsr\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
+/*
+** test_lshift_right_int_si:
+** lsr\t(w[0-9]+), w0, 4
+** lsr\tw0, \1, w1
+** ret
+*/
Int64x1
test_ashift_right_int_di (Int64x1 b, Int64x1 c)
@@ -166,8 +211,12 @@ test_ashift_right_int_di (Int64x1 b, Int64x1 c)
a = a >> c;
return a;
}
-/* { dg-final { scan-assembler "asr\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
-/* { dg-final { scan-assembler "asr\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
+/*
+** test_ashift_right_int_di:
+** asr\t(x[0-9]+), x0, 8
+** asr\tx0, \1, x1
+** ret
+*/
Int32x1
test_ashift_right_int_si (Int32x1 b, Int32x1 c)
@@ -178,8 +227,12 @@ test_ashift_right_int_si (Int32x1 b, Int32x1 c)
a = a >> c;
return a;
}
-/* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
-/* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
+/*
+** test_ashift_right_int_si:
+** asr\t(w[0-9]+), w0, 4
+** asr\tw0, \1, w1
+** ret
+*/
#define CHECK(var,val) \
do \
@@ -225,4 +278,3 @@ main ()
return 0;
}
-
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_5.c
b/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_5.c
index 4f39b675bff..1b725275782 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_5.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/fold_to_highpart_5.c
@@ -68,8 +68,8 @@
/* { dg-final { scan-assembler-times {ssubl2\t} 3} } */
/* { dg-final { scan-assembler-times {usubl2\t} 3} } */
-/* { dg-final { scan-assembler-times {sabdl2\t} 3} } */
-/* { dg-final { scan-assembler-times {uabdl2\t} 3} } */
+/* { dg-final { scan-assembler-times {sabal2\t} 3} } */
+/* { dg-final { scan-assembler-times {uabal2\t} 3} } */
/* { dg-final { scan-assembler-times {saddw2\t} 3} } */
/* { dg-final { scan-assembler-times {uaddw2\t} 3} } */
diff --git a/gcc/testsuite/gcc.target/aarch64/singleton_intrinsics_1.c
b/gcc/testsuite/gcc.target/aarch64/singleton_intrinsics_1.c
index 1f21bd33e73..27360150b58 100644
--- a/gcc/testsuite/gcc.target/aarch64/singleton_intrinsics_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/singleton_intrinsics_1.c
@@ -298,7 +298,7 @@ test_vrsra_n_s64 (int64x1_t a, int64x1_t b)
return vrsra_n_s64 (a, b, 3);
}
-/* { dg-final { scan-assembler-times "\\tsrsra\\td\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "\\tursra\\td\[0-9\]+" 1 } } */
uint64x1_t
test_vrsra_n_u64 (uint64x1_t a, uint64x1_t b)
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/arith_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/arith_1.c
index c2e1f6c7eae..785b4cc9335 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/arith_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/arith_1.c
@@ -85,7 +85,7 @@ DO_ARITH_OPS (int64_t, -, minus)
/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.d, z[0-9]+\.d, #-1\n} } }
*/
/* { dg-final { scan-assembler-times {\tsub\tz[0-9]+\.d, z[0-9]+\.d, #1\n} 1 }
} */
-/* { dg-final { scan-assembler-not {\tsub\tz[0-9]+\.b, z[0-9]+\.b, #1\n} } } */
+/* Asserted above { scan-assembler-not {\tsub\tz[0-9]+\.b, z[0-9]+\.b, #1\n} }
*/
/* { dg-final { scan-assembler-not {\tsub\tz[0-9]+\.b, z[0-9]+\.b, #5\n} } } */
/* { dg-final { scan-assembler-not {\tsub\tz[0-9]+\.b, z[0-9]+\.b, #255\n} } }
*/
/* { dg-final { scan-assembler-not {\tsub\tz[0-9]+\.b, z[0-9]+\.b, #256\n} } }
*/
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_1.c
index d0db0900ece..e68d5a4a237 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_1.c
@@ -38,10 +38,6 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
z[0-9]+\.s, #1\.0\n} 1 } } */
/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
z[0-9]+\.d, #1\.0\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m,
z[0-9]+\.h, #1\.0\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
z[0-9]+\.s, #1\.0\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
z[0-9]+\.d, #1\.0\n} 1 } } */
-
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_3.c
b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_3.c
index 741f8f6d08e..0ef89914b8b 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_3.c
@@ -47,8 +47,8 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s,
z[0-9]+\.s\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d,
z[0-9]+\.d\n} 3 } } */
/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
/* { dg-final { scan-assembler-not {\tmov\tz} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5.c
b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5.c
index 4bae7e02de4..836cd2c067e 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_5.c
@@ -11,10 +11,6 @@
/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
z[0-9]+\.s, #1\.0\n} 1 } } */
/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
z[0-9]+\.d, #1\.0\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m,
z[0-9]+\.h, #1\.0\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m,
z[0-9]+\.s, #1\.0\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
z[0-9]+\.d, #1\.0\n} 1 } } */
-
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7.c
b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7.c
index 30f07f62ddb..9331d9e5ccf 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmaxnm_7.c
@@ -20,8 +20,8 @@
/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m,
z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s,
z[0-9]+\.s\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d,
z[0-9]+\.d\n} 3 } } */
/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
/* { dg-final { scan-assembler-not {\tmov\tz} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_1.c
index d667b20884e..f6f58391621 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_1.c
@@ -12,10 +12,6 @@
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
z[0-9]+\.s, #1\.0\n} 1 } } */
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
z[0-9]+\.d, #1\.0\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m,
z[0-9]+\.h, #1\.0\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
z[0-9]+\.s, #1\.0\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
z[0-9]+\.d, #1\.0\n} 1 } } */
-
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_3.c
b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_3.c
index d39dd1825bd..01d96ec1eb7 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_3.c
@@ -21,8 +21,8 @@
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s,
z[0-9]+\.s\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d,
z[0-9]+\.d\n} 3 } } */
/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
/* { dg-final { scan-assembler-not {\tmov\tz} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5.c
b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5.c
index 290c4beac24..9865f08818a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_5.c
@@ -12,10 +12,6 @@
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
z[0-9]+\.s, #1\.0\n} 1 } } */
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
z[0-9]+\.d, #1\.0\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m,
z[0-9]+\.h, #1\.0\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m,
z[0-9]+\.s, #1\.0\n} 1 } } */
-/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
z[0-9]+\.d, #1\.0\n} 1 } } */
-
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7.c
b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7.c
index 347a1a3540b..eae52cd284c 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fminnm_7.c
@@ -21,8 +21,8 @@
/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m,
z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s,
z[0-9]+\.s\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d,
z[0-9]+\.d\n} 3 } } */
/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
/* { dg-final { scan-assembler-not {\tmov\tz} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_3.c
b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_3.c
index 4da147e1568..549950d2e15 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fmul_3.c
@@ -43,8 +43,8 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.d, p[0-7]/m,
z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s,
z[0-9]+\.s\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d,
z[0-9]+\.d\n} 3 } } */
/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
/* { dg-final { scan-assembler-not {\tmov\tz} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_fsubr_3.c
b/gcc/testsuite/gcc.target/aarch64/sve/cond_fsubr_3.c
index 328af5741ef..91eee805bbb 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_fsubr_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_fsubr_3.c
@@ -43,8 +43,8 @@ TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.d, p[0-7]/m,
z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
-/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h,
z[0-9]+\.h\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s,
z[0-9]+\.s\n} 3 } } */
+/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d,
z[0-9]+\.d\n} 3 } } */
/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
/* { dg-final { scan-assembler-not {\tmov\tz} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/mixed_size_6.c
b/gcc/testsuite/gcc.target/aarch64/sve/mixed_size_6.c
index 837edecf7d0..da778204454 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/mixed_size_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/mixed_size_6.c
@@ -39,9 +39,9 @@ f3 (uint64_t *restrict ptr1, uint32_t *restrict ptr2,
uint32_t start)
}
/* { dg-final { scan-assembler {\tindex\tz[0-9]+\.d, x[0-9]+, #1\n} } } */
-/* { dg-final { scan-assembler {\tindex\tz[0-9]+\.d, x[0-9]+, #1\n} } } */
+/* { dg-final { scan-assembler {\tindex\tz[0-9]+\.d, x[0-9]+, #2\n} } } */
/* { dg-final { scan-assembler {\tindex\tz[0-9]+\.d, x[0-9]+, #4\n} } } */
/* { dg-final { scan-assembler-not {\tindex\tz[0-9]+\.d, w[0-9]+, #1\n} } } */
-/* { dg-final { scan-assembler-not {\tindex\tz[0-9]+\.d, w[0-9]+, #1\n} } } */
+/* { dg-final { scan-assembler-not {\tindex\tz[0-9]+\.d, w[0-9]+, #2\n} } } */
/* { dg-final { scan-assembler-not {\tindex\tz[0-9]+\.d, w[0-9]+, #4\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/annotate_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/pcs/annotate_1.c
index a85d068607a..6430980add4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/annotate_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/annotate_1.c
@@ -96,7 +96,6 @@ svfloat64x4_t ret_f64x4 (void) { return svundef4_f64 (); }
/* { dg-final { scan-assembler {\t\.variant_pcs\tret_s8x3\n} } } */
/* { dg-final { scan-assembler {\t\.variant_pcs\tret_s16x3\n} } } */
-/* { dg-final { scan-assembler {\t\.variant_pcs\tret_s16x3\n} } } */
/* { dg-final { scan-assembler {\t\.variant_pcs\tret_s32x3\n} } } */
/* { dg-final { scan-assembler {\t\.variant_pcs\tret_s64x3\n} } } */
/* { dg-final { scan-assembler {\t\.variant_pcs\tret_u8x3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6.c
b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6.c
index 81c0a4163fa..bf7308dd567 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6.c
@@ -55,7 +55,7 @@ CALLEE (s8, svint8_t)
CALLEE (u8, svuint8_t)
/*
-** callee_u8:
+** callee_mf8:
** (
** ld1 ({v.*}), \[x0\]
** st1 \1, \[x8\]
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/struct_move_3.c
b/gcc/testsuite/gcc.target/aarch64/sve/struct_move_3.c
index 19011384f9b..d6092e791d8 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/struct_move_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/struct_move_3.c
@@ -37,7 +37,7 @@ typedef struct { vnx2df a[4]; } vnx8df;
TEST_TYPE (vnx64qi, z0, z4)
TEST_TYPE (vnx32hi, z6, z2)
TEST_TYPE (vnx16si, z12, z16)
-TEST_TYPE (vnx8di, z17, z13)
+TEST_TYPE (vnx8di, z17, z12)
TEST_TYPE (vnx32hf, z18, z1)
TEST_TYPE (vnx16sf, z20, z16)
TEST_TYPE (vnx8df, z24, z28)
@@ -92,11 +92,11 @@ TEST_TYPE (vnx8df, z24, z28)
/* { dg-final { scan-assembler {\tld1d\tz19.d, p[0-7]/z, \[x0, #2, mul vl\]\n}
} } */
/* { dg-final { scan-assembler {\tld1d\tz20.d, p[0-7]/z, \[x0, #3, mul vl\]\n}
} } */
/* { dg-final { scan-assembler { test vnx8di 1 z17\n} } } */
-/* { dg-final { scan-assembler {\tmov\tz13.d, z17.d\n} } } */
-/* { dg-final { scan-assembler {\tmov\tz14.d, z18.d\n} } } */
-/* { dg-final { scan-assembler {\tmov\tz15.d, z19.d\n} } } */
-/* { dg-final { scan-assembler {\tmov\tz16.d, z20.d\n} } } */
-/* { dg-final { scan-assembler { test vnx8di 2 z17, z17, z13\n} } } */
+/* { dg-final { scan-assembler {\tmov\tz12.d, z17.d\n} } } */
+/* { dg-final { scan-assembler {\tmov\tz13.d, z18.d\n} } } */
+/* { dg-final { scan-assembler {\tmov\tz14.d, z19.d\n} } } */
+/* { dg-final { scan-assembler {\tmov\tz15.d, z20.d\n} } } */
+/* { dg-final { scan-assembler { test vnx8di 2 z17, z17, z12\n} } } */
/* { dg-final { scan-assembler {\tst1d\tz17.d, p[0-7], \[x0, #4, mul vl\]\n} }
} */
/* { dg-final { scan-assembler {\tst1d\tz18.d, p[0-7], \[x0, #5, mul vl\]\n} }
} */
/* { dg-final { scan-assembler {\tst1d\tz19.d, p[0-7], \[x0, #6, mul vl\]\n} }
} */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/struct_move_6.c
b/gcc/testsuite/gcc.target/aarch64/sve/struct_move_6.c
index 8336e3f1edd..12b714481e3 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/struct_move_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/struct_move_6.c
@@ -34,7 +34,7 @@ typedef struct { vnx2df a[4]; } vnx8df;
TEST_TYPE (vnx64qi, z0, z4)
TEST_TYPE (vnx32hi, z6, z2)
TEST_TYPE (vnx16si, z12, z16)
-TEST_TYPE (vnx8di, z17, z13)
+TEST_TYPE (vnx8di, z17, z12)
TEST_TYPE (vnx16sf, z20, z16)
TEST_TYPE (vnx8df, z24, z28)
@@ -88,11 +88,11 @@ TEST_TYPE (vnx8df, z24, z28)
/* { dg-final { scan-assembler {\tldr\tz19, \[x0, #2, mul vl\]\n} } } */
/* { dg-final { scan-assembler {\tldr\tz20, \[x0, #3, mul vl\]\n} } } */
/* { dg-final { scan-assembler { test vnx8di 1 z17\n} } } */
-/* { dg-final { scan-assembler {\tmov\tz13.d, z17.d\n} } } */
-/* { dg-final { scan-assembler {\tmov\tz14.d, z18.d\n} } } */
-/* { dg-final { scan-assembler {\tmov\tz15.d, z19.d\n} } } */
-/* { dg-final { scan-assembler {\tmov\tz16.d, z20.d\n} } } */
-/* { dg-final { scan-assembler { test vnx8di 2 z17, z17, z13\n} } } */
+/* { dg-final { scan-assembler {\tmov\tz12.d, z17.d\n} } } */
+/* { dg-final { scan-assembler {\tmov\tz13.d, z18.d\n} } } */
+/* { dg-final { scan-assembler {\tmov\tz14.d, z19.d\n} } } */
+/* { dg-final { scan-assembler {\tmov\tz15.d, z20.d\n} } } */
+/* { dg-final { scan-assembler { test vnx8di 2 z17, z17, z12\n} } } */
/* { dg-final { scan-assembler {\tstr\tz17, \[x0, #4, mul vl\]\n} } } */
/* { dg-final { scan-assembler {\tstr\tz18, \[x0, #5, mul vl\]\n} } } */
/* { dg-final { scan-assembler {\tstr\tz19, \[x0, #6, mul vl\]\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/uzp1_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/uzp1_1.c
index 84c6c6f1c60..83451db9b44 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/uzp1_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/uzp1_1.c
@@ -32,9 +32,6 @@ UZP1 (vnx8hf, ((vnx8hi) { 0, 2, 4, 6, 8, 10, 12, 14,
16, 18, 20, 22, 24, 26, 28, 30 }));
/* { dg-final { scan-assembler-not {\ttbl\t} } } */
-/* { dg-final { scan-assembler-not {\ttbl\t} } } */
-/* { dg-final { scan-assembler-not {\ttbl\t} } } */
-/* { dg-final { scan-assembler-not {\ttbl\t} } } */
/* { dg-final { scan-assembler-times {\tuzp1\tz[0-9]+\.d, z[0-9]+\.d,
z[0-9]+\.d\n} 2 } } */
/* { dg-final { scan-assembler-times {\tuzp1\tz[0-9]+\.s, z[0-9]+\.s,
z[0-9]+\.s\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/uzp2_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/uzp2_1.c
index 1336cafc5c7..bfdee4073f7 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/uzp2_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/uzp2_1.c
@@ -31,9 +31,6 @@ UZP2 (vnx8hf, ((vnx8hi) { 1, 3, 5, 7, 9, 11, 13, 15,
17, 19, 21, 23, 25, 27, 29, 31 }));
/* { dg-final { scan-assembler-not {\ttbl\t} } } */
-/* { dg-final { scan-assembler-not {\ttbl\t} } } */
-/* { dg-final { scan-assembler-not {\ttbl\t} } } */
-/* { dg-final { scan-assembler-not {\ttbl\t} } } */
/* { dg-final { scan-assembler-times {\tuzp2\tz[0-9]+\.d, z[0-9]+\.d,
z[0-9]+\.d\n} 2 } } */
/* { dg-final { scan-assembler-times {\tuzp2\tz[0-9]+\.s, z[0-9]+\.s,
z[0-9]+\.s\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/vector-compare-5.c
b/gcc/testsuite/gcc.target/aarch64/vector-compare-5.c
index a1a601dc195..7becd56f10c 100644
--- a/gcc/testsuite/gcc.target/aarch64/vector-compare-5.c
+++ b/gcc/testsuite/gcc.target/aarch64/vector-compare-5.c
@@ -53,15 +53,13 @@ n (v4i *x, v4i const *y, v4i *z, v4i *t)
}
+/* { dg-final { scan-tree-dump-times
"\\s*\\*tD\\.\\d+\\s*=\\s*\\{\\s*-1(?:,\\s*-1){3}\\s*\\}\\s*;" 1 "original" } }
*/
+/* { dg-final { scan-tree-dump-times
"\\s*\\*tD\\.\\d+\\s*=\\s*\\{\\s*0(?:,\\s*0){3}\\s*\\}\\s*;" 3 "original" } } */
+/* { dg-final { scan-tree-dump-times
"\\s*\\*zD\\.\\d+\\s*=\\s*\\{\\s*-1(?:,\\s*-1){3}\\s*\\}\\s*;" 2 "original" } }
*/
+
/* { dg-final { scan-tree-dump
".*\\*zD\\.\\d+\\s*=\\s*VEC_COND_EXPR\\s*<\\s*\\*xD\\.\\d+\\s*>=\\s*VIEW_CONVERT_EXPR<v4iD\\.\\d+>\\(\\*yD\\.\\d+\\)\\s*,\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*,\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*>\\s*;"
"original" } } */
-/* { dg-final { scan-tree-dump
".*\\*tD\\.\\d+\\s*=\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*;" "original" } } */
/* { dg-final { scan-tree-dump
".*\\*zD\\.\\d+\\s*=\\s*VEC_COND_EXPR\\s*<\\s*\\*xD\\.\\d+\\s*==\\s*VIEW_CONVERT_EXPR<v4iD\\.\\d+>\\(\\*yD\\.\\d+\\)\\s*,\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*,\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*>\\s*;"
"original" } } */
/* { dg-final { scan-tree-dump
".*\\*tD\\.\\d+\\s*=\\s*VEC_COND_EXPR\\s*<\\s*\\*xD\\.\\d+\\s*<\\s*VIEW_CONVERT_EXPR<v4iD\\.\\d+>\\(\\*yD\\.\\d+\\)\\s*,\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*,\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*>\\s*;"
"original" } } */
-/* { dg-final { scan-tree-dump
".*\\*zD\\.\\d+\\s*=\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*;" "original" } } */
-/* { dg-final { scan-tree-dump
".*\\*tD\\.\\d+\\s*=\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*;" "original" } } */
/* { dg-final { scan-tree-dump
".*\\*zD\\.\\d+\\s*=\\s*VEC_COND_EXPR\\s*<\\s*\\*xD\\.\\d+\\s*<=\\s*VIEW_CONVERT_EXPR<v4iD\\.\\d+>\\(\\*yD\\.\\d+\\)\\s*,\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*,\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*>\\s*;"
"original" } } */
-/* { dg-final { scan-tree-dump
".*\\*tD\\.\\d+\\s*=\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*;" "original" } } */
/* { dg-final { scan-tree-dump
".*\\*zD\\.\\d+\\s*=\\s*VEC_COND_EXPR\\s*<\\s*\\*xD\\.\\d+\\s*!=\\s*VIEW_CONVERT_EXPR<v4iD\\.\\d+>\\(\\*yD\\.\\d+\\)\\s*,\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*,\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*>\\s*;"
"original" } } */
/* { dg-final { scan-tree-dump
".*\\*tD\\.\\d+\\s*=\\s*VEC_COND_EXPR\\s*<\\s*\\*xD\\.\\d+\\s*>=\\s*VIEW_CONVERT_EXPR<v4iD\\.\\d+>\\(\\*yD\\.\\d+\\)\\s*,\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*,\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*>\\s*;"
"original" } } */
-/* { dg-final { scan-tree-dump
".*\\*zD\\.\\d+\\s*=\\s*\\{\\s*-1(,\\s*-1){3}\\s*\\}\\s*;" "original" } } */
-/* { dg-final { scan-tree-dump
".*\\*tD\\.\\d+\\s*=\\s*\\{\\s*0(,\\s*0){3}\\s*\\}\\s*;" "original" } } */
--
2.43.0
