On 9/4/25 8:28 AM, Paul-Antoine Arras wrote:
This is a slightly amended patch that fixes modes and instruction type
attribute. Here is the relevant snippet:
diff --git gcc/config/riscv/autovec-opt.md gcc/config/riscv/autovec-opt.md
index d4335dc04ba..67f4d9ce3a8 100644
--- gcc/config/riscv/autovec-opt.md
+++ gcc/config/riscv/autovec-opt.md
@@ -2146,3 +2146,26 @@ (define_insn_and_split
"*v<ieee_fmaxmin_op>_vf_<mode>"
}
[(set_attr "type" "vfminmax")]
)
+
+;; vfwmul.vf
+(define_insn_and_split "*vfwmul_vf_<mode>"
+ [(set (match_operand:VWEXTF 0 "register_operand")
+ (mult:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand:<V_DOUBLE_TRUNC> 1 "register_operand"))
+ (vec_duplicate:VWEXTF
+ (float_extend:<VEL>
+ (match_operand:<VSUBEL> 2 "register_operand")))))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ riscv_vector::emit_vlmax_insn (code_for_pred_dual_widen_scalar (MULT,
+ <MODE>mode),
+ riscv_vector::BINARY_OP_FRM_DYN,
operands);
+
+ DONE;
+ }
+ [(set_attr "type" "vfwmul")]
+)
diff --git gcc/config/riscv/vector.md gcc/config/riscv/vector.md
index 2b35d66b611..187d207318c 100644
--- gcc/config/riscv/vector.md
+++ gcc/config/riscv/vector.md
@@ -7296,8 +7296,8 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
(any_widen_binop:VWEXTF
(float_extend:VWEXTF
(match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "
vr, vr"))
- (float_extend:VWEXTF
- (vec_duplicate:<V_DOUBLE_TRUNC>
+ (vec_duplicate:VWEXTF
+ (float_extend:<VEL>
(match_operand:<VSUBEL> 4 "register_operand" "
f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" "
vu, 0")))]
"TARGET_VECTOR"
Thanks,
PA
On 03/09/2025 16:52, Paul-Antoine Arras wrote:
This pattern enables the combine pass (or late-combine, depending on
the case)
to merge a float_extend'ed vec_duplicate into a mult RTL instruction.
Before this patch, we have six instructions, e.g.:
fcvt.d.s fa0,fa0
vsetvli a5,zero,e64,m1,ta,ma
vfmv.v.f v3,fa0
vfwcvt.f.f.v v1,v2
vsetvli zero,zero,e64,m1,ta,ma
vfmul.vv v1,v3,v1
After, we get only one:
vfwmul.vf v1,v2,fa0
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*vfwmul_vf_<mode>): New pattern to
combine float_extend + vec_duplicate + vfmul.vv into vfmul.vf.
* config/riscv/vector.md (*@pred_dual_widen_<optab><mode>_scalar):
Swap operands to match the RTL emitted by expand, i.e. first
float_extend then vec_duplicate.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfwmul.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h: Add support for
widening variants.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_widen_run.h: New test
helper.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmul-run-1-f16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmul-run-1-f32.c: New test.
OK (updated version)
jeff
