Hi, For Zvfhmin a vector mode exists but the corresponding vec_extract does not. This patch checks that a vec_extract is available and otherwise falls back to standard handling.
I cannot test myself right now so handing it off to the CI :) Regards Robin PR target/121510 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_move): Check if we can vec_extract. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr121510.c: New test. --- gcc/config/riscv/riscv.cc | 3 ++- .../gcc.target/riscv/rvv/autovec/pr121510.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121510.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index d5a656c3781..07d40f459e3 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3686,7 +3686,8 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) not enabled. In that case we just want to let the standard expansion path run. */ if (riscv_vector::get_vector_mode (smode, nunits).exists (&vmode) - && gen_lowpart_common (vmode, SUBREG_REG (src))) + && gen_lowpart_common (vmode, SUBREG_REG (src)) + && convert_optab_handler (vec_extract_optab, vmode, smode)) { rtx v = gen_lowpart (vmode, SUBREG_REG (src)); rtx int_reg = dest; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121510.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121510.c new file mode 100644 index 00000000000..b5d02116c98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121510.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfhmin -O3" } */ + +long *print_bfloat_block; +void ftoastr(float); +void print_bfloat() { + for (;;) { + long j; + union { + _Float16 x; + char b[] + } u; + j = 0; + for (; j < sizeof 0; j++) + u.b[j] = print_bfloat_block[j]; + ftoastr(u.x); + } +} -- 2.51.0