在 2025/9/4 下午7:48, Lulu Cheng 写道:
在 2025/8/22 下午4:14, Xi Ruoyao 写道:
In a CAS operation, even if expected != *memory we still need to do an
atomic load of *memory into output. But I made a mistake in the initial
implementation, causing the output to contain junk in this situation.
Like a normal atomic load, the atomic load embedded in the CAS semantic
is required to work on read-only page. Thus we cannot rely on sc.q to
ensure the atomicity of the load. Use LSX to perform the load instead,
and also use LSX to compare the 16B values to keep the ll-sc loop body
short.
Hi,Ruoyao:
This modification will successfully compile
atomic-compare-exchange-5.c at -O0,
but will cause ICE when optimization is turned on O1 or higher.
diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
index 2ee400e2381..66a431ddbf0 100644
--- a/gcc/config/loongarch/sync.md
+++ b/gcc/config/loongarch/sync.md
@@ -682,21 +682,25 @@ (define_expand "atomic_compare_and_swap<mode>"
})
(define_insn "atomic_compare_and_swapti_scq"
- [(set (match_operand:TI 0 "register_operand" "=&r")
- (match_operand:TI 1 "memory_operand" "+ZB"))
+ [(set (match_operand:V2DI 0 "register_operand" "=&f")
+ (match_operand:V2DI 1 "memory_operand" "+m"))
(set (match_dup 1)
- (unspec_volatile:TI [(match_operand:TI 2 "reg_or_0_operand" "rJ")
- (match_operand:TI 3 "reg_or_0_operand" "rJ")
- (match_operand:SI 4 "const_int_operand")] ;; mod_f
- UNSPEC_COMPARE_AND_SWAP))
- (clobber (match_scratch:DI 5 "=&r"))]
- "TARGET_64BIT && ISA_HAS_SCQ"
+ (unspec_volatile:V2DI
+ [(match_operand:V2DI 2 "reg_or_0_operand" "fJ")
+ (match_operand:TI 3 "reg_or_0_operand" "rJ")
+ (match_operand:SI 4 "const_int_operand")]
+ UNSPEC_COMPARE_AND_SWAP))
+ (set (match_operand:FCC 5 "register_operand" "=z")
+ (ne:FCC (match_dup 1) (match_dup 3)))
Operands[2] should be used here instead of operands[3]:
(ne:FCC (match_dup 1) (match_dup 2)))
