Re: [PATCH v1 1/2] AArch64: Add `+sme-lutv2` flag

[Saurabh Jha]

On 9/3/2025 1:33 PM, Karl Meakin wrote:

On 03/09/2025 09:26, Saurabh Jha wrote:

Hi Karl,

I think the component tags in the subject line, AArch64, in this example, should be lowercase so maybe use it like "aarch64:". Its not something documented but just something I have seen in other places.

It would also be helpful to have a short summary in the body of the email which will be included in the commit message. Something along the lines of "Add support for +sme-lutv2 which enables support for the SME LUTv2 instructions".

You also need to add to the new flag at `gcc/doc/invoke.texi` file.

I will address these in the next revision in the series

More comments inline.

On 9/2/2025 3:16 PM, Karl Meakin wrote:

gcc/ChangeLog:

    * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Conditonally define

    `__ARM_FEATURE_SME_LUTv2" macro.

    * config/aarch64/aarch64-option-extensions.def (AARCH64_OPT_EXTENSION("sme-lutv2")): New

    optional architecture extension.
    * config/aarch64/aarch64.h (TARGET_SME_LUTv2): New macro.
---
  gcc/config/aarch64/aarch64-c.cc                  | 1 +
  gcc/config/aarch64/aarch64-option-extensions.def | 2 ++
  gcc/config/aarch64/aarch64.h                     | 7 ++++++-
  3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/ aarch64-c.cc

index 98337b7f693..a8ff58e4994 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -269,6 +269,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
              "__ARM_FEATURE_SVE_BF16", pfile);
      aarch64_def_or_undef (TARGET_LUT, "__ARM_FEATURE_LUT", pfile);

+  aarch64_def_or_undef (TARGET_SME_LUTv2, "__ARM_FEATURE_SME_LUTv2", pfile);

      aarch64_def_or_undef (TARGET_FP8, "__ARM_FEATURE_FP8", pfile);

  diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/ gcc/config/aarch64/aarch64-option-extensions.def

index db88df08a6a..a70375c053f 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def

@@ -277,6 +277,8 @@ AARCH64_OPT_EXTENSION("ssve-fp8dot2", SSVE_FP8DOT2, (SME2, FP8), (), (), "smesf8

    AARCH64_OPT_EXTENSION("lut", LUT, (SIMD), (), (), "lut")

  +AARCH64_OPT_EXTENSION ("sme-lutv2", SME_LUTv2, (SME2), (), (), "sme-lutv2")

+
  AARCH64_OPT_EXTENSION("cpa", CPA, (), (), (), "")
    #undef AARCH64_OPT_FMV_EXTENSION
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 2b3610c86ed..899abb8e9df 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h

@@ -477,9 +477,14 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED

     enabled through +faminmax.  */
  #define TARGET_FAMINMAX AARCH64_HAVE_ISA (FAMINMAX)

  -/* Lookup table (LUTI) extension instructions are enabled through +lut.  */ +/* Lookup table (LUTI) extension instructions with 2-bit indices and 2-bit

+   indices are enabled through +lut.  */

Should this be "2-bit indices and 4-bit indices"? Or even "2-bit and 4-bit indices"?>   #define TARGET_LUT AARCH64_HAVE_ISA (LUT)

Yes, that is a typo. Thank you for catching it, I will address in the next revision.

  +/* Lookup table (LUTI) extension instructions with 4-bit indices and 8-bit

+   elements are enabled through +sme-lutv2.  */

How about "4-bit and 8-bit indices?" Unless I am misunderstanding something and 8-bit elements are actually a thing.

The wording "4-bit elements and 8-bit elements" was copied directly from the ACLE (https://arm-software.github.io/acle/main/acle.html#lookup- table-extensions).

Oh okay, that's good then. Thank you for the clarification.

8-bit elements are indeed a thing. ARM, C9.2.141:

Lookup table read with 4-bit indexes and 8-bit elements (four registers)

This instruction copies 8-bit elements from ZT0 to four destination vectors using packed 4-bit indices in the two source

vectors.

+ #define TARGET_SME_LUTv2 AARCH64_HAVE_ISA (SME_LUTv2)
+
  /* Prefer different predicate registers for the output of a predicated
     operation over re-using an existing input predicate.  */
  #define TARGET_SVE_PRED_CLOBBER (TARGET_SVE \

Thanks,
Saurabh