On 9/1/25 5:07 AM, Paul-Antoine Arras wrote:
This pattern enables the combine pass (or late-combine, depending on the case)
to merge a vec_duplicate into an smax RTL instruction.
[ ... ]
diff --git gcc/config/riscv/autovec-opt.md gcc/config/riscv/autovec-opt.md
index 9695fdcb5c9..d56fb5f237c 100644
--- gcc/config/riscv/autovec-opt.md
+++ gcc/config/riscv/autovec-opt.md
@@ -2144,3 +2144,22 @@ (define_insn_and_split "*vfmin_vf_ieee_<mode>"
}
[(set_attr "type" "vfminmax")]
)
+
+;; vfmax.vf
+(define_insn_and_split "*vfmax_vf_<mode>"
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (smax:V_VLSF
+ (vec_duplicate:V_VLSF
+ (match_operand:<VEL> 2 "register_operand"))
+ (match_operand:V_VLSF 1 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ riscv_vector::emit_vlmax_insn (code_for_pred_scalar (SMAX, <MODE>mode),
+ riscv_vector::BINARY_OP, operands);
+ DONE;
+ }
+ [(set_attr "type" "vfminmax")]
So much like the IEEE variant that Kito commented on, this may be best
folded into the recently added vfmin_vf_<mode> pattern. You'd want to
use an iterator on the code that expands to smin/smax and a
corresponding change to to the emit_vlmax_insn call.
OK with that change.
jeff
