From: Pan Li <pan2...@intel.com>
The form 4 of unsigned scalar SAT_MUL is covered in middle-expand
alreay, add test case here to cover form 4.
The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat/sat_u_mul-5-u16-from-u128.c: New test.
* gcc.target/riscv/sat/sat_u_mul-5-u16-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv32.c: New test.
* gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv64.c: New test.
* gcc.target/riscv/sat/sat_u_mul-5-u32-from-u128.c: New test.
* gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv32.c: New test.
* gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv64.c: New test.
* gcc.target/riscv/sat/sat_u_mul-5-u64-from-u128.c: New test.
* gcc.target/riscv/sat/sat_u_mul-5-u8-from-u128.c: New test.
* gcc.target/riscv/sat/sat_u_mul-5-u8-from-u16.c: New test.
* gcc.target/riscv/sat/sat_u_mul-5-u8-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv32.c: New test.
* gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv64.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u128.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u64.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u128.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u64.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-5-u64-from-u128.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u128.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u16.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u64.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat/sat_arith.h | 17 +++++++++++++++++
.../riscv/sat/sat_u_mul-5-u16-from-u128.c | 11 +++++++++++
.../riscv/sat/sat_u_mul-5-u16-from-u32.c | 11 +++++++++++
.../riscv/sat/sat_u_mul-5-u16-from-u64.rv32.c | 11 +++++++++++
.../riscv/sat/sat_u_mul-5-u16-from-u64.rv64.c | 11 +++++++++++
.../riscv/sat/sat_u_mul-5-u32-from-u128.c | 11 +++++++++++
.../riscv/sat/sat_u_mul-5-u32-from-u64.rv32.c | 11 +++++++++++
.../riscv/sat/sat_u_mul-5-u32-from-u64.rv64.c | 11 +++++++++++
.../riscv/sat/sat_u_mul-5-u64-from-u128.c | 11 +++++++++++
.../riscv/sat/sat_u_mul-5-u8-from-u128.c | 11 +++++++++++
.../riscv/sat/sat_u_mul-5-u8-from-u16.c | 11 +++++++++++
.../riscv/sat/sat_u_mul-5-u8-from-u32.c | 11 +++++++++++
.../riscv/sat/sat_u_mul-5-u8-from-u64.rv32.c | 11 +++++++++++
.../riscv/sat/sat_u_mul-5-u8-from-u64.rv64.c | 11 +++++++++++
.../riscv/sat/sat_u_mul-run-5-u16-from-u128.c | 16 ++++++++++++++++
.../riscv/sat/sat_u_mul-run-5-u16-from-u32.c | 16 ++++++++++++++++
.../riscv/sat/sat_u_mul-run-5-u16-from-u64.c | 16 ++++++++++++++++
.../riscv/sat/sat_u_mul-run-5-u32-from-u128.c | 16 ++++++++++++++++
.../riscv/sat/sat_u_mul-run-5-u32-from-u64.c | 16 ++++++++++++++++
.../riscv/sat/sat_u_mul-run-5-u64-from-u128.c | 16 ++++++++++++++++
.../riscv/sat/sat_u_mul-run-5-u8-from-u128.c | 16 ++++++++++++++++
.../riscv/sat/sat_u_mul-run-5-u8-from-u16.c | 16 ++++++++++++++++
.../riscv/sat/sat_u_mul-run-5-u8-from-u32.c | 16 ++++++++++++++++
.../riscv/sat/sat_u_mul-run-5-u8-from-u64.c | 16 ++++++++++++++++
24 files changed, 320 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u64-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u128.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u64-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u64.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
index 8ef50e9c6b6..035545c9e0f 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
@@ -724,4 +724,21 @@ sat_u_mul_##NT##_from_##WT##_fmt_3 (NT a, NT b) \
sat_u_mul_##NT##_from_##WT##_fmt_3 (a, b)
#define RUN_SAT_U_MUL_FMT_3_WRAP(NT, WT, a, b) RUN_SAT_U_MUL_FMT_3(NT, WT, a,
b)
+#define DEF_SAT_U_MUL_FMT_4(NT, WT) \
+NT __attribute__((noinline)) \
+sat_u_mul_##NT##_from_##WT##_fmt_4 (NT a, NT b) \
+{ \
+ WT x = (WT)a * (WT)b; \
+ NT max = -1; \
+ if (x >= (WT)(max)) \
+ return max; \
+ else \
+ return (NT)x; \
+}
+
+#define DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT) DEF_SAT_U_MUL_FMT_4(NT, WT)
+#define RUN_SAT_U_MUL_FMT_4(NT, WT, a, b) \
+ sat_u_mul_##NT##_from_##WT##_fmt_4 (a, b)
+#define RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, a, b) RUN_SAT_U_MUL_FMT_4(NT, WT, a,
b)
+
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u128.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u128.c
new file mode 100644
index 00000000000..d3cef166ca2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u128.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
+
+#include "sat_arith.h"
+
+#define NT uint16_t
+#define WT uint128_t
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u32.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u32.c
new file mode 100644
index 00000000000..d7e735636f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u32.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
+
+#include "sat_arith.h"
+
+#define NT uint16_t
+#define WT uint32_t
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv32.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv32.c
new file mode 100644
index 00000000000..7533823f914
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv32.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc -mabi=ilp32 -fdump-tree-optimized" } */
+
+#include "sat_arith.h"
+
+#define NT uint16_t
+#define WT uint64_t
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv64.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv64.c
new file mode 100644
index 00000000000..ae4f8c08ccd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv64.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
+
+#include "sat_arith.h"
+
+#define NT uint16_t
+#define WT uint64_t
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u128.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u128.c
new file mode 100644
index 00000000000..037497c5603
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u128.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
+
+#include "sat_arith.h"
+
+#define NT uint32_t
+#define WT uint128_t
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv32.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv32.c
new file mode 100644
index 00000000000..f10cd40d9a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv32.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc -mabi=ilp32 -fdump-tree-optimized" } */
+
+#include "sat_arith.h"
+
+#define NT uint32_t
+#define WT uint64_t
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv64.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv64.c
new file mode 100644
index 00000000000..6229f511108
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv64.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
+
+#include "sat_arith.h"
+
+#define NT uint32_t
+#define WT uint64_t
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u64-from-u128.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u64-from-u128.c
new file mode 100644
index 00000000000..e852851274b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u64-from-u128.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
+
+#include "sat_arith.h"
+
+#define NT uint64_t
+#define WT uint128_t
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u128.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u128.c
new file mode 100644
index 00000000000..4ae5c8cb87a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u128.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
+
+#include "sat_arith.h"
+
+#define NT uint8_t
+#define WT uint128_t
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u16.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u16.c
new file mode 100644
index 00000000000..2580c23ae27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u16.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
+
+#include "sat_arith.h"
+
+#define NT uint8_t
+#define WT uint16_t
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u32.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u32.c
new file mode 100644
index 00000000000..43ca2c747a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u32.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
+
+#include "sat_arith.h"
+
+#define NT uint8_t
+#define WT uint32_t
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv32.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv32.c
new file mode 100644
index 00000000000..c5b84cc76b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv32.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc -mabi=ilp32 -fdump-tree-optimized" } */
+
+#include "sat_arith.h"
+
+#define NT uint8_t
+#define WT uint64_t
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv64.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv64.c
new file mode 100644
index 00000000000..51a27a223b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv64.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
+
+#include "sat_arith.h"
+
+#define NT uint8_t
+#define WT uint64_t
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u128.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u128.c
new file mode 100644
index 00000000000..ec23d81c6cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u128.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { rv64 } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define NT uint16_t
+#define WT uint128_t
+#define NAME usmul
+#define DATA TEST_BINARY_DATA_WRAP(NT, NAME)
+#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME)
+#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y)
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+#include "scalar_sat_binary_run_xxx.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u32.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u32.c
new file mode 100644
index 00000000000..e175988888d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { rv32 || rv64 } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define NT uint16_t
+#define WT uint32_t
+#define NAME usmul
+#define DATA TEST_BINARY_DATA_WRAP(NT, NAME)
+#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME)
+#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y)
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+#include "scalar_sat_binary_run_xxx.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u64.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u64.c
new file mode 100644
index 00000000000..5d4e28b97ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { rv32 || rv64 } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define NT uint16_t
+#define WT uint64_t
+#define NAME usmul
+#define DATA TEST_BINARY_DATA_WRAP(NT, NAME)
+#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME)
+#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y)
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+#include "scalar_sat_binary_run_xxx.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u128.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u128.c
new file mode 100644
index 00000000000..d8beb8f2fa5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u128.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { rv64 } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define NT uint32_t
+#define WT uint128_t
+#define NAME usmul
+#define DATA TEST_BINARY_DATA_WRAP(NT, NAME)
+#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME)
+#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y)
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+#include "scalar_sat_binary_run_xxx.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u64.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u64.c
new file mode 100644
index 00000000000..afc9c9ace59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { rv32 || rv64 } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define NT uint32_t
+#define WT uint64_t
+#define NAME usmul
+#define DATA TEST_BINARY_DATA_WRAP(NT, NAME)
+#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME)
+#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y)
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+#include "scalar_sat_binary_run_xxx.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u64-from-u128.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u64-from-u128.c
new file mode 100644
index 00000000000..d5f20f54425
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u64-from-u128.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { rv64 } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define NT uint64_t
+#define WT uint128_t
+#define NAME usmul
+#define DATA TEST_BINARY_DATA_WRAP(NT, NAME)
+#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME)
+#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y)
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+#include "scalar_sat_binary_run_xxx.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u128.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u128.c
new file mode 100644
index 00000000000..9d445412a1a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u128.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { rv64 } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define NT uint8_t
+#define WT uint128_t
+#define NAME usmul
+#define DATA TEST_BINARY_DATA_WRAP(NT, NAME)
+#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME)
+#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y)
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+#include "scalar_sat_binary_run_xxx.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u16.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u16.c
new file mode 100644
index 00000000000..cd520876b68
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { rv32 || rv64 } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define NT uint8_t
+#define WT uint16_t
+#define NAME usmul
+#define DATA TEST_BINARY_DATA_WRAP(NT, NAME)
+#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME)
+#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y)
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+#include "scalar_sat_binary_run_xxx.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u32.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u32.c
new file mode 100644
index 00000000000..f6ae1879493
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { rv32 || rv64 } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define NT uint8_t
+#define WT uint32_t
+#define NAME usmul
+#define DATA TEST_BINARY_DATA_WRAP(NT, NAME)
+#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME)
+#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y)
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+#include "scalar_sat_binary_run_xxx.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u64.c
b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u64.c
new file mode 100644
index 00000000000..f94cc9daf2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { rv32 || rv64 } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define NT uint8_t
+#define WT uint64_t
+#define NAME usmul
+#define DATA TEST_BINARY_DATA_WRAP(NT, NAME)
+#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME)
+#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_4_WRAP(NT, WT, x, y)
+
+DEF_SAT_U_MUL_FMT_4_WRAP(NT, WT)
+
+#include "scalar_sat_binary_run_xxx.h"
--
2.43.0
