If we implement bare QI/HImode cbranch, mov<ALLI>cc will
ask aarch64_gen_compare_reg for a QI/HImode compare,
which we cannot provide without modification elsewhere.
However, we can usually get the extensions for free from
surrounding operations. So e.g. CBcond in SImode is more
generally compact than CBBcond, since it also accepts some
immediate operands.
Therefore, force cbranch expansion through a wider mode,
leaving the CBB/CBH pattern in place for the optimizer
in case it can make use of it.
gcc:
* config/aarch64/aarch64.md (cbranch<SHORT>4): Remove.
(aarch64_cb<INT_CMP><SHORT>): Name with *.
---
gcc/config/aarch64/aarch64.md | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 2fffd175b96..012c4a2430f 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -768,16 +768,6 @@
}
)
-(define_expand "cbranch<SHORT:mode>4"
- [(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
- [(match_operand:SHORT 1 "register_operand")
- (match_operand:SHORT 2 "aarch64_reg_or_zero")])
- (label_ref (match_operand 3))
- (pc)))]
- "TARGET_CMPBR"
- ""
-)
-
(define_expand "cbranch<mode>4"
[(set (pc) (if_then_else
(match_operator 0 "aarch64_comparison_operator"
@@ -913,7 +903,7 @@
)
;; Emit a `CBB<cond> (register)` or `CBH<cond> (register)` instruction.
-(define_insn "aarch64_cb<INT_CMP:code><SHORT:mode>"
+(define_insn "*aarch64_cb<INT_CMP:code><SHORT:mode>"
[(set (pc) (if_then_else (INT_CMP
(match_operand:SHORT 0 "register_operand" "r")
(match_operand:SHORT 1 "aarch64_reg_or_zero" "rZ"))
--
2.43.0
