Hello!
After discussion with Oleg, it looks that it is enough to prevent
wrong registers in the output of the (multi-output) insn pattern. As
far as inputs are concerned, combine already handles limited reload
classes in the right way. The problem with x86 is, that reload tried
to fix output operand of the multi-output ins, where scheduler already
moved load of ax register before this insn.
Version 2 of the patch now handles only output operands. Also,
handling of empty constraints was fixed.
2012-08-18 Uros Bizjak <ubiz...@gmail.com>
PR rtl-optimization/46829
* combine.c (recog_for_combine): Check operand constraints
to reject instructions where wrong hard registers were propagated
into output operands.
testsuite/ChangeLog:
2012-08-18 Uros Bizjak <ubiz...@gmail.com>
PR rtl-optimization/46829
* gcc.target/i386/pr46829.c: New test.
Patch was bootstrapped and regression tested on
x86_64-unknown-linux-gnu {,-m32}.
Uros.
Index: combine.c
===================================================================
--- combine.c (revision 190500)
+++ combine.c (working copy)
@@ -10507,6 +10507,7 @@ recog_for_combine (rtx *pnewpat, rtx insn, rtx *pn
int i;
rtx notes = 0;
rtx old_notes, old_pat;
+ int old_icode;
/* If PAT is a PARALLEL, check to see if it contains the CLOBBER
we use to indicate that something didn't match. If we find such a
@@ -10566,6 +10567,7 @@ recog_for_combine (rtx *pnewpat, rtx insn, rtx *pn
print_rtl_single (dump_file, pat);
}
}
+
PATTERN (insn) = old_pat;
REG_NOTES (insn) = old_notes;
@@ -10607,6 +10609,93 @@ recog_for_combine (rtx *pnewpat, rtx insn, rtx *pn
pat = newpat;
}
+ old_pat = PATTERN (insn);
+ old_notes = REG_NOTES (insn);
+ old_icode = INSN_CODE (insn);
+ PATTERN (insn) = pat;
+ REG_NOTES (insn) = notes;
+
+ /* Check operand constraints in case wrong hard registers were
+ propagated into output operands of insn pattern. These invalid
+ insns can eventually confuse reload to error out with a
+ spill failure. See also PR 46829. */
+ if (insn_code_number >= 0
+ && insn_code_number != NOOP_MOVE_INSN_CODE
+ && (INSN_CODE (insn) = recog (PATTERN (insn), insn, 0)) >= 0)
+ {
+ extract_insn (insn);
+ preprocess_constraints ();
+
+ for (i = 0; i < recog_data.n_operands; i++)
+ {
+ rtx op;
+ enum machine_mode mode;
+ struct operand_alternative *op_alt;
+ int offset = 0;
+ bool win;
+ int j;
+
+ if (recog_data.operand_type[i] == OP_IN)
+ continue;
+
+ op = recog_data.operand[i];
+ mode = GET_MODE (op);
+
+ /* A unary operator may be accepted by the predicate, but it
+ is irrelevant for matching constraints. */
+ if (UNARY_P (op))
+ op = XEXP (op, 0);
+
+ if (GET_CODE (op) == SUBREG)
+ {
+ if (REG_P (SUBREG_REG (op))
+ && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
+ offset = subreg_regno_offset (REGNO (SUBREG_REG (op)),
+ GET_MODE (SUBREG_REG (op)),
+ SUBREG_BYTE (op),
+ GET_MODE (op));
+ op = SUBREG_REG (op);
+ }
+
+ if (!(REG_P (op) && HARD_REGISTER_P (op)))
+ continue;
+
+ op_alt = recog_op_alt[i];
+
+ /* Operand has no constraints, anything is OK. */
+ win = !recog_data.n_alternatives;
+
+ for (j = 0; j < recog_data.n_alternatives; j++)
+ {
+ if (op_alt[j].anything_ok
+ || (op_alt[j].matches != -1
+ && reg_fits_class_p (op,
recog_op_alt[op_alt[j].matches][j].cl,
+ offset, mode))
+ || reg_fits_class_p (op, op_alt[j].cl, offset, mode))
+ {
+ win = true;
+ break;
+ }
+ }
+
+ if (!win)
+ {
+ if (dump_file && (dump_flags & TDF_DETAILS))
+ {
+ fputs ("Operand failed to match constraints:\n",
+ dump_file);
+ print_rtl_single (dump_file, recog_data.operand[i]);
+ }
+ insn_code_number = -1;
+ break;
+ }
+ }
+ }
+
+ PATTERN (insn) = old_pat;
+ REG_NOTES (insn) = old_notes;
+ INSN_CODE (insn) = old_icode;
+
*pnewpat = pat;
*pnotes = notes;
