On Wed, Jul 16, 2025 at 1:13 AM Takayuki 'January June' Suwa
<jjsuwa_sys3...@yahoo.co.jp> wrote:
>
> This patch fixes the following defects in the function:
>
> - The cost of move instructions larger than the natural word width,
> specifically "movd[if]_internal", cannot be estimated correctly
> - Floating-point or symbolic constant assignment insns cannot be
> identified as L32R instructions
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_is_insn_L32R_p):
> Rewrite to capture insns that could be L32R machine instructions
> wherever possible.
> (xtensa_rtx_costs): Fix to consider that moves larger than a
> natural word can take multiple L32R machine instructions.
> (constantpool_address_p): Cosmetics.
> * config/xtensa/xtensa.md (movdi_internal, movdf_internal):
> Add missing insn attributes.
> ---
> gcc/config/xtensa/xtensa.cc | 44 ++++++++++++++++++++-----------------
> gcc/config/xtensa/xtensa.md | 10 +++++++--
> 2 files changed, 32 insertions(+), 22 deletions(-)
Regtested for target=xtensa-linux-uclibc. Two new regressions in the
configuration
with call0 ABI:
FAIL: gcc.c-torture/execute/20000603-1.c -O2 execution test
FAIL: gcc.c-torture/execute/20000603-1.c -O3 -g execution test
because the load from b->d is now scheduled before the store to a->d:
f:
addi sp, sp, -16
l32r a5, .LC2
s32i.n a0, sp, 12
+ mov.n a9, a2
movi.n a4, 0
- s32i.n a4, a2, 0
- s32i.n a5, a2, 4
- l32r a9, .LC1
l32i.n a2, a3, 0
l32i.n a3, a3, 4
+ s32i.n a4, a9, 0
+ s32i.n a5, a9, 4
+ l32r a9, .LC1
callx0 a9
l32i.n a0, sp, 12
addi sp, sp, 16
ret.n
which may be expected with -O2 and -O3 that enable -fstrict-aliasing.
Committed to master.
--
Thanks.
-- Max
