[PATCH v1 0/5] RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost

[pan2 . li]

From: Pan Li <pan2...@intel.com>

This patch would like to introduce the combine of vec_dup + vaaddu.vv
into vaaddu.vx on the cost value of GR2VR.  The late-combine will take
place if the cost of GR2VR is zero, or reject the combine if non-zero
like 1, 2, 15 in test.  There will be two cases for the combine:

Case 0:
 |   ...
 |   vmv.v.x
 | L1:
 |   vaaddu.vv
 |   J L1
 |   ...

Case 1:
 |   ...
 | L1:
 |   vmv.v.x
 |   vaaddu.vv
 |   J L1
 |   ...

Both will be combined to below if the cost of GR2VR is zero.
 |   ...
 | L1:
 |   vaaddu.vx
 |   J L1
 |   ...

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.

Pan Li (5):
  RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, 
QI and SI mode
  RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 0 with GR2VR cost 
0, 2 and 15 for QI, HI and SI mode
  RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 1 with GR2VR cost 
0, 1 and 2 for QI, HI and SI mode
  RISC-V: Allow VLS DImode for sat_op vx DImode pattern
  RISC-V: Add test for vec_duplicate + vaaddu.vv combine for DImode

 gcc/config/riscv/autovec-opt.md               |  62 ++++++
 gcc/config/riscv/riscv.cc                     |  29 ++-
 gcc/config/riscv/vector.md                    |  30 +--
 .../riscv/rvv/autovec/vx_vf/vx-1-u16.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-1-u32.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-1-u64.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-1-u8.c         |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-u16.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-u32.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-u64.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-u8.c         |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-u16.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-u32.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-u64.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-u8.c         |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-4-u16.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-4-u32.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-4-u64.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-4-u8.c         |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-5-u16.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-5-u32.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-5-u64.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-5-u8.c         |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-6-u16.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-6-u32.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-6-u64.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-6-u8.c         |   2 +
 .../riscv/rvv/autovec/vx_vf/vx_binary.h       |  56 +++--
 .../riscv/rvv/autovec/vx_vf/vx_binary_data.h  | 196 ++++++++++++++++++
 .../rvv/autovec/vx_vf/vx_vaadd-run-1-u16.c    |  17 ++
 .../rvv/autovec/vx_vf/vx_vaadd-run-1-u32.c    |  17 ++
 .../rvv/autovec/vx_vf/vx_vaadd-run-1-u64.c    |  17 ++
 .../rvv/autovec/vx_vf/vx_vaadd-run-1-u8.c     |  17 ++
 33 files changed, 445 insertions(+), 32 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u16.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u64.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u8.c

-- 
2.43.0