From: panciyan <[email protected]>
This patch adds testcase for form11 and form12, as shown below:
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_11 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
out[i] = overflow ? 0 : ret; \
} \
}
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_12 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
out[i] = !overflow ? ret : 0; \
} \
}
Passed the rv64gcv regression test.
Signed-off-by: Ciyan Pan <[email protected]>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: Add unsigned vector
SAT_SUB form11 and form12.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c: New test.
---
.../riscv/rvv/autovec/sat/vec_sat_arith.h | 30 ++++++++
.../rvv/autovec/sat/vec_sat_u_sub-11-u16.c | 9 +++
.../rvv/autovec/sat/vec_sat_u_sub-11-u32.c | 9 +++
.../rvv/autovec/sat/vec_sat_u_sub-11-u64.c | 9 +++
.../rvv/autovec/sat/vec_sat_u_sub-11-u8.c | 9 +++
.../rvv/autovec/sat/vec_sat_u_sub-12-u16.c | 9 +++
.../rvv/autovec/sat/vec_sat_u_sub-12-u32.c | 9 +++
.../rvv/autovec/sat/vec_sat_u_sub-12-u64.c | 9 +++
.../rvv/autovec/sat/vec_sat_u_sub-12-u8.c | 9 +++
.../autovec/sat/vec_sat_u_sub-run-11-u16.c | 75 +++++++++++++++++++
.../autovec/sat/vec_sat_u_sub-run-11-u32.c | 75 +++++++++++++++++++
.../autovec/sat/vec_sat_u_sub-run-11-u64.c | 75 +++++++++++++++++++
.../rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c | 75 +++++++++++++++++++
.../autovec/sat/vec_sat_u_sub-run-12-u16.c | 75 +++++++++++++++++++
.../autovec/sat/vec_sat_u_sub-run-12-u32.c | 75 +++++++++++++++++++
.../autovec/sat/vec_sat_u_sub-run-12-u64.c | 75 +++++++++++++++++++
.../rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c | 75 +++++++++++++++++++
17 files changed, 702 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
index f78bdc047ca..da38b00017a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
@@ -511,6 +511,36 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2,
unsigned limit) \
} \
}
+#define DEF_VEC_SAT_U_SUB_FMT_11(T) \
+void __attribute__((noinline)) \
+vec_sat_u_sub_##T##_fmt_11 (T *out, T *op_1, T *op_2, unsigned limit) \
+{ \
+ unsigned i; \
+ for (i = 0; i < limit; i++) \
+ { \
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ T ret; \
+ T overflow = __builtin_sub_overflow (x, y, &ret); \
+ out[i] = overflow ? 0 : ret; \
+ } \
+}
+
+#define DEF_VEC_SAT_U_SUB_FMT_12(T) \
+void __attribute__((noinline)) \
+vec_sat_u_sub_##T##_fmt_12 (T *out, T *op_1, T *op_2, unsigned limit) \
+{ \
+ unsigned i; \
+ for (i = 0; i < limit; i++) \
+ { \
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ T ret; \
+ T overflow = __builtin_sub_overflow (x, y, &ret); \
+ out[i] = !overflow ? ret : 0; \
+ } \
+}
+
#define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c
new file mode 100644
index 00000000000..a1c5c19aea1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_FMT_11(uint8_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c
new file mode 100644
index 00000000000..b5264a323c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_FMT_11(uint32_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c
new file mode 100644
index 00000000000..1a68b5c0426
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_FMT_11(uint64_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c
new file mode 100644
index 00000000000..a1c5c19aea1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_FMT_11(uint8_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c
new file mode 100644
index 00000000000..fd987e9d588
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_FMT_12(uint16_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c
new file mode 100644
index 00000000000..bc380feb3d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_FMT_12(uint32_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c
new file mode 100644
index 00000000000..c03163f9a1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_FMT_12(uint64_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c
new file mode 100644
index 00000000000..91e190969e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_FMT_12(uint8_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c
new file mode 100644
index 00000000000..ac54be09040
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c
@@ -0,0 +1,75 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define T uint16_t
+#define N 16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_11
+
+DEF_VEC_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3][N] = {
+ {
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* arg_0 */
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* arg_1 */
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* expect */
+ },
+ {
+ {
+ 65535, 65535, 65535, 65535,
+ 65535, 65535, 65535, 65535,
+ 65535, 65535, 65535, 65535,
+ 65535, 65535, 65535, 65535,
+ },
+ {
+ 55535, 45535, 35535, 25535,
+ 55535, 45535, 35535, 25535,
+ 55535, 45535, 35535, 25535,
+ 55535, 45535, 35535, 25535,
+ },
+ {
+ 10000, 20000, 30000, 40000,
+ 10000, 20000, 30000, 40000,
+ 10000, 20000, 30000, 40000,
+ 10000, 20000, 30000, 40000,
+ },
+ },
+ {
+ {
+ 0, 0, 1, 0,
+ 1, 2, 3, 0,
+ 1, 65535, 3, 65535,
+ 5, 65534, 65535, 9,
+ },
+ {
+ 0, 1, 1, 65534,
+ 65534, 65534, 1, 65535,
+ 0, 65535, 65535, 0,
+ 65535, 65535, 1, 2,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 2, 0,
+ 1, 0, 0, 65535,
+ 0, 0, 65534, 7,
+ },
+ },
+};
+
+#include "vec_sat_binary_vvv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c
new file mode 100644
index 00000000000..db85ec813a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c
@@ -0,0 +1,75 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define T uint32_t
+#define N 16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_11
+
+DEF_VEC_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3][N] = {
+ {
+ {
+ 0, 0, 4, 0,
+ 0, 0, 4, 0,
+ 0, 0, 4, 0,
+ 0, 0, 4, 0,
+ }, /* arg_0 */
+ {
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ }, /* arg_1 */
+ {
+ 0, 0, 2, 0,
+ 0, 0, 2, 0,
+ 0, 0, 2, 0,
+ 0, 0, 2, 0,
+ }, /* expect */
+ },
+ {
+ {
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ },
+ {
+ 1294967295, 2294967295, 3294967295, 4294967295,
+ 1294967295, 2294967295, 3294967295, 4294967295,
+ 1294967295, 2294967295, 3294967295, 4294967295,
+ 1294967295, 2294967295, 3294967295, 4294967295,
+ },
+ {
+ 3000000000, 2000000000, 1000000000, 0,
+ 3000000000, 2000000000, 1000000000, 0,
+ 3000000000, 2000000000, 1000000000, 0,
+ 3000000000, 2000000000, 1000000000, 0,
+ },
+ },
+ {
+ {
+ 0, 0, 9, 0,
+ 1, 4294967295, 3, 0,
+ 1, 2, 3, 4,
+ 5, 4294967294, 4294967295, 4294967295,
+ },
+ {
+ 0, 1, 1, 4294967294,
+ 1, 2, 4294967294, 4294967295,
+ 1, 4294967295, 4294967295, 1,
+ 1, 4294967295, 4294967290, 9,
+ },
+ {
+ 0, 0, 8, 0,
+ 0, 4294967293, 0, 0,
+ 0, 0, 0, 3,
+ 4, 0, 5, 4294967286,
+ },
+ },
+};
+
+#include "vec_sat_binary_vvv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c
new file mode 100644
index 00000000000..266fc5731b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c
@@ -0,0 +1,75 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define T uint64_t
+#define N 16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_11
+
+DEF_VEC_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3][N] = {
+ {
+ {
+ 0, 9, 0, 0,
+ 0, 9, 0, 0,
+ 0, 9, 0, 0,
+ 0, 9, 0, 0,
+ }, /* arg_0 */
+ {
+ 0, 2, 3, 1,
+ 0, 2, 3, 1,
+ 0, 2, 3, 1,
+ 0, 2, 3, 1,
+ }, /* arg_1 */
+ {
+ 0, 7, 0, 0,
+ 0, 7, 0, 0,
+ 0, 7, 0, 0,
+ 0, 7, 0, 0,
+ }, /* expect */
+ },
+ {
+ {
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
18446744073709551615u,
+ },
+ {
+ 10446744073709551615u, 11446744073709551615u, 12446744073709551615u,
18446744073709551615u,
+ 10446744073709551615u, 11446744073709551615u, 12446744073709551615u,
18446744073709551615u,
+ 10446744073709551615u, 11446744073709551615u, 12446744073709551615u,
18446744073709551615u,
+ 10446744073709551615u, 11446744073709551615u, 12446744073709551615u,
18446744073709551615u,
+ },
+ {
+ 8000000000000000000u, 7000000000000000000u, 6000000000000000000u,
0u,
+ 8000000000000000000u, 7000000000000000000u, 6000000000000000000u,
0u,
+ 8000000000000000000u, 7000000000000000000u, 6000000000000000000u,
0u,
+ 8000000000000000000u, 7000000000000000000u, 6000000000000000000u,
0u,
+ },
+ },
+ {
+ {
+ 0, 18446744073709551615u, 1,
0,
+ 1, 18446744073709551615u, 3,
0,
+ 1, 18446744073709551614u, 3,
4,
+ 5, 18446744073709551614u, 18446744073709551615u,
9,
+ },
+ {
+ 0, 1, 1,
18446744073709551614u,
+ 18446744073709551614u, 18446744073709551614u, 18446744073709551614u,
18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
1,
+ },
+ {
+ 0, 18446744073709551614u, 0,
0,
+ 0, 1, 0,
0,
+ 0, 0, 0,
0,
+ 0, 0, 0,
8,
+ },
+ },
+};
+
+#include "vec_sat_binary_vvv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c
new file mode 100644
index 00000000000..a0d80c6a589
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c
@@ -0,0 +1,75 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define T uint8_t
+#define N 16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_11
+
+DEF_VEC_SAT_U_SUB_FMT_11(T)
+
+T test_data[][3][N] = {
+ {
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* arg_0 */
+ {
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ }, /* arg_1 */
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* expect */
+ },
+ {
+ {
+ 0, 255, 255, 255,
+ 0, 255, 255, 255,
+ 0, 255, 255, 255,
+ 0, 255, 255, 255,
+ },
+ {
+ 1, 255, 254, 251,
+ 1, 255, 254, 251,
+ 1, 255, 254, 251,
+ 1, 255, 254, 251,
+ },
+ {
+ 0, 0, 1, 4,
+ 0, 0, 1, 4,
+ 0, 0, 1, 4,
+ 0, 0, 1, 4,
+ },
+ },
+ {
+ {
+ 0, 0, 1, 0,
+ 1, 2, 3, 0,
+ 1, 2, 3, 255,
+ 5, 254, 255, 9,
+ },
+ {
+ 0, 1, 0, 254,
+ 254, 254, 254, 255,
+ 255, 255, 0, 252,
+ 255, 255, 255, 1,
+ },
+ {
+ 0, 0, 1, 0,
+ 0, 0, 0, 0,
+ 0, 0, 3, 3,
+ 0, 0, 0, 8,
+ },
+ },
+};
+
+#include "vec_sat_binary_vvv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c
new file mode 100644
index 00000000000..c6a3571520f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c
@@ -0,0 +1,75 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define T uint16_t
+#define N 16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_12
+
+DEF_VEC_SAT_U_SUB_FMT_12(T)
+
+T test_data[][3][N] = {
+ {
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* arg_0 */
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* arg_1 */
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* expect */
+ },
+ {
+ {
+ 65535, 65535, 65535, 65535,
+ 65535, 65535, 65535, 65535,
+ 65535, 65535, 65535, 65535,
+ 65535, 65535, 65535, 65535,
+ },
+ {
+ 55535, 45535, 35535, 25535,
+ 55535, 45535, 35535, 25535,
+ 55535, 45535, 35535, 25535,
+ 55535, 45535, 35535, 25535,
+ },
+ {
+ 10000, 20000, 30000, 40000,
+ 10000, 20000, 30000, 40000,
+ 10000, 20000, 30000, 40000,
+ 10000, 20000, 30000, 40000,
+ },
+ },
+ {
+ {
+ 0, 0, 1, 0,
+ 1, 2, 3, 0,
+ 1, 65535, 3, 65535,
+ 5, 65534, 65535, 9,
+ },
+ {
+ 0, 1, 1, 65534,
+ 65534, 65534, 1, 65535,
+ 0, 65535, 65535, 0,
+ 65535, 65535, 1, 2,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 2, 0,
+ 1, 0, 0, 65535,
+ 0, 0, 65534, 7,
+ },
+ },
+};
+
+#include "vec_sat_binary_vvv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c
new file mode 100644
index 00000000000..461e553ae63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c
@@ -0,0 +1,75 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define T uint32_t
+#define N 16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_12
+
+DEF_VEC_SAT_U_SUB_FMT_12(T)
+
+T test_data[][3][N] = {
+ {
+ {
+ 0, 0, 4, 0,
+ 0, 0, 4, 0,
+ 0, 0, 4, 0,
+ 0, 0, 4, 0,
+ }, /* arg_0 */
+ {
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ }, /* arg_1 */
+ {
+ 0, 0, 2, 0,
+ 0, 0, 2, 0,
+ 0, 0, 2, 0,
+ 0, 0, 2, 0,
+ }, /* expect */
+ },
+ {
+ {
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ },
+ {
+ 1294967295, 2294967295, 3294967295, 4294967295,
+ 1294967295, 2294967295, 3294967295, 4294967295,
+ 1294967295, 2294967295, 3294967295, 4294967295,
+ 1294967295, 2294967295, 3294967295, 4294967295,
+ },
+ {
+ 3000000000, 2000000000, 1000000000, 0,
+ 3000000000, 2000000000, 1000000000, 0,
+ 3000000000, 2000000000, 1000000000, 0,
+ 3000000000, 2000000000, 1000000000, 0,
+ },
+ },
+ {
+ {
+ 0, 0, 9, 0,
+ 1, 4294967295, 3, 0,
+ 1, 2, 3, 4,
+ 5, 4294967294, 4294967295, 4294967295,
+ },
+ {
+ 0, 1, 1, 4294967294,
+ 1, 2, 4294967294, 4294967295,
+ 1, 4294967295, 4294967295, 1,
+ 1, 4294967295, 4294967290, 9,
+ },
+ {
+ 0, 0, 8, 0,
+ 0, 4294967293, 0, 0,
+ 0, 0, 0, 3,
+ 4, 0, 5, 4294967286,
+ },
+ },
+};
+
+#include "vec_sat_binary_vvv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c
new file mode 100644
index 00000000000..fe50f972204
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c
@@ -0,0 +1,75 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define T uint64_t
+#define N 16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_12
+
+DEF_VEC_SAT_U_SUB_FMT_12(T)
+
+T test_data[][3][N] = {
+ {
+ {
+ 0, 9, 0, 0,
+ 0, 9, 0, 0,
+ 0, 9, 0, 0,
+ 0, 9, 0, 0,
+ }, /* arg_0 */
+ {
+ 0, 2, 3, 1,
+ 0, 2, 3, 1,
+ 0, 2, 3, 1,
+ 0, 2, 3, 1,
+ }, /* arg_1 */
+ {
+ 0, 7, 0, 0,
+ 0, 7, 0, 0,
+ 0, 7, 0, 0,
+ 0, 7, 0, 0,
+ }, /* expect */
+ },
+ {
+ {
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
18446744073709551615u,
+ },
+ {
+ 10446744073709551615u, 11446744073709551615u, 12446744073709551615u,
18446744073709551615u,
+ 10446744073709551615u, 11446744073709551615u, 12446744073709551615u,
18446744073709551615u,
+ 10446744073709551615u, 11446744073709551615u, 12446744073709551615u,
18446744073709551615u,
+ 10446744073709551615u, 11446744073709551615u, 12446744073709551615u,
18446744073709551615u,
+ },
+ {
+ 8000000000000000000u, 7000000000000000000u, 6000000000000000000u,
0u,
+ 8000000000000000000u, 7000000000000000000u, 6000000000000000000u,
0u,
+ 8000000000000000000u, 7000000000000000000u, 6000000000000000000u,
0u,
+ 8000000000000000000u, 7000000000000000000u, 6000000000000000000u,
0u,
+ },
+ },
+ {
+ {
+ 0, 18446744073709551615u, 1,
0,
+ 1, 18446744073709551615u, 3,
0,
+ 1, 18446744073709551614u, 3,
4,
+ 5, 18446744073709551614u, 18446744073709551615u,
9,
+ },
+ {
+ 0, 1, 1,
18446744073709551614u,
+ 18446744073709551614u, 18446744073709551614u, 18446744073709551614u,
18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u, 18446744073709551615u,
1,
+ },
+ {
+ 0, 18446744073709551614u, 0,
0,
+ 0, 1, 0,
0,
+ 0, 0, 0,
0,
+ 0, 0, 0,
8,
+ },
+ },
+};
+
+#include "vec_sat_binary_vvv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c
new file mode 100644
index 00000000000..218c5d18d4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c
@@ -0,0 +1,75 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define T uint8_t
+#define N 16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_12
+
+DEF_VEC_SAT_U_SUB_FMT_12(T)
+
+T test_data[][3][N] = {
+ {
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* arg_0 */
+ {
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ 0, 1, 2, 3,
+ }, /* arg_1 */
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, /* expect */
+ },
+ {
+ {
+ 0, 255, 255, 255,
+ 0, 255, 255, 255,
+ 0, 255, 255, 255,
+ 0, 255, 255, 255,
+ },
+ {
+ 1, 255, 254, 251,
+ 1, 255, 254, 251,
+ 1, 255, 254, 251,
+ 1, 255, 254, 251,
+ },
+ {
+ 0, 0, 1, 4,
+ 0, 0, 1, 4,
+ 0, 0, 1, 4,
+ 0, 0, 1, 4,
+ },
+ },
+ {
+ {
+ 0, 0, 1, 0,
+ 1, 2, 3, 0,
+ 1, 2, 3, 255,
+ 5, 254, 255, 9,
+ },
+ {
+ 0, 1, 0, 254,
+ 254, 254, 254, 255,
+ 255, 255, 0, 252,
+ 255, 255, 255, 1,
+ },
+ {
+ 0, 0, 1, 0,
+ 0, 0, 0, 0,
+ 0, 0, 3, 3,
+ 0, 0, 0, 8,
+ },
+ },
+};
+
+#include "vec_sat_binary_vvv_run.h"
--
2.17.1
