From 55ff76120047c0a072c3f2a668bc62a4e0772d4c Mon Sep 17 00:00:00 2001 From: Kuan-Lin Chen Date: Wed, 7 May 2025 16:20:35 +0800 Subject: [PATCH 4/7] RISC-V: Add support for the XAndesvbfhcvt ISA extension. This patch add support for XAndesvbfhcvt ISA extension. This extension defines instructions to perform vector floating-point conversion between the BFLOAT16 floating-point data and the IEEE-754 32-bit single-precision floating-point (SP) data in a vector register. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Turn on VECTOR_ELEN_BF_16 for XAndesvbfhcvt. * config.gcc: Add extra_objs andes-vector-builtins-bases.o and extra_headers andes_vector.h. * config/riscv/riscv-vector-builtins.cc (f32_to_bf16_nf_w_ops): New operand information. (f32_to_bf16_nf_w_ops): New operand information. (DEF_RVV_FUNCTION): New def. * config/riscv/riscv-vector-builtins.def (bf16_s): Ditto. (s_bf16): Ditto. * config/riscv/riscv-vector-builtins.h (enum required_ext): Ditto. (required_ext_to_isa_name): Add case XANDESVBFHCVT_EXT. (required_extensions_specified): Ditto. * config/riscv/t-riscv: Add andes-vector-builtins-functions.def, andes-vector-builtins-bases.h and andes-vector-builtins-bases.o. * config/riscv/vector-iterators.md (NDS_VWEXTBF): New iterator. (NDS_V_DOUBLE_TRUNC_BF): New attr. * config/riscv/andes-vector-builtins-bases.cc: New file. * config/riscv/andes-vector-builtins-bases.h: New file. * config/riscv/andes-vector-builtins-functions.def: New file. * config/riscv/andes_vector.h: New file. * config/riscv/andes_vector.md: New file. * config/riscv/vector.md: Include andes_vector.md. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: * gcc.target/riscv/rvv/xandesvector/nds_vfwcvt.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config.gcc | 4 +- .../riscv/andes-vector-builtins-bases.cc | 103 ++++++++++++++++++ .../riscv/andes-vector-builtins-bases.h | 33 ++++++ .../riscv/andes-vector-builtins-functions.def | 45 ++++++++ gcc/config/riscv/andes-vector.md | 51 +++++++++ gcc/config/riscv/andes_vector.h | 32 ++++++ gcc/config/riscv/riscv-vector-builtins.cc | 21 ++++ gcc/config/riscv/riscv-vector-builtins.def | 2 + gcc/config/riscv/riscv-vector-builtins.h | 5 + gcc/config/riscv/t-riscv | 15 +++ gcc/config/riscv/vector-iterators.md | 13 +++ gcc/config/riscv/vector.md | 1 + gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 + .../riscv/rvv/xandesvector/nds_vfwcvt.c | 37 +++++++ 15 files changed, 364 insertions(+), 2 deletions(-) create mode 100644 gcc/config/riscv/andes-vector-builtins-bases.cc create mode 100644 gcc/config/riscv/andes-vector-builtins-bases.h create mode 100644 gcc/config/riscv/andes-vector-builtins-functions.def create mode 100644 gcc/config/riscv/andes-vector.md create mode 100644 gcc/config/riscv/andes_vector.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xandesvector/nds_vfwcvt.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 3c25848ccd38..240dff7f6df0 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -1512,6 +1512,8 @@ static const riscv_extra_ext_flag_table_t riscv_extra_ext_flag_table[] = RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_isa_flags, MASK_FULL_V), RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_isa_flags, MASK_VECTOR), + RISCV_EXT_FLAG_ENTRY ("xandesvbfhcvt", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_BF_16), + {NULL, NULL, NULL, 0} }; diff --git a/gcc/config.gcc b/gcc/config.gcc index a6f6efec4e10..87803acfa97a 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -549,10 +549,10 @@ riscv*) cpu_type=riscv extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-string.o" extra_objs="${extra_objs} riscv-v.o riscv-vsetvl.o riscv-vector-costs.o riscv-avlprop.o riscv-vect-permconst.o" - extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o sifive-vector-builtins-bases.o" + extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o sifive-vector-builtins-bases.o andes-vector-builtins-bases.o" extra_objs="${extra_objs} thead.o riscv-target-attr.o riscv-zicfilp.o" d_target_objs="riscv-d.o" - extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h riscv_th_vector.h sifive_vector.h" + extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h riscv_th_vector.h sifive_vector.h andes_vector.h" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h" extra_options="${extra_options} riscv/riscv-ext.opt" diff --git a/gcc/config/riscv/andes-vector-builtins-bases.cc b/gcc/config/riscv/andes-vector-builtins-bases.cc new file mode 100644 index 000000000000..69e16fd94543 --- /dev/null +++ b/gcc/config/riscv/andes-vector-builtins-bases.cc @@ -0,0 +1,103 @@ +/* function_base implementation for Andes custom 'V' Extension for GNU compiler. + Copyright (C) 2024-2025 Free Software Foundation, Inc. + Contributed by Andes. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" +#include "tree.h" +#include "rtl.h" +#include "tm_p.h" +#include "memmodel.h" +#include "insn-codes.h" +#include "optabs.h" +#include "recog.h" +#include "expr.h" +#include "basic-block.h" +#include "function.h" +#include "fold-const.h" +#include "gimple.h" +#include "gimple-iterator.h" +#include "gimplify.h" +#include "explow.h" +#include "emit-rtl.h" +#include "tree-vector-builder.h" +#include "rtx-vector-builder.h" +#include "riscv-vector-builtins.h" +#include "riscv-vector-builtins-shapes.h" +#include "andes-vector-builtins-bases.h" +#include "riscv-vector-builtins-bases.h" + +using namespace riscv_vector; + +namespace riscv_vector { + +/* Implements Andes vfwcvt. */ +class nds_vfwcvt : public function_base +{ +public: + bool apply_tail_policy_p () const override { return false; } + bool apply_mask_policy_p () const override { return false; } + bool use_mask_predication_p () const override { return false; } + bool has_merge_operand_p () const override { return false; } + bool can_be_overloaded_p (enum predication_type_index) const override + { + return false; + } + + rtx expand (function_expander &e) const override + { + e.add_input_operand (0); + return e.generate_insn (code_for_nds_vfwcvt_bf16 (e.vector_mode ())); + } +}; + +class nds_vfncvt : public function_base +{ +public: + + bool apply_tail_policy_p () const override { return false; } + bool apply_mask_policy_p () const override { return false; } + bool use_mask_predication_p () const override { return false; } + bool has_merge_operand_p () const override { return false; } + bool can_be_overloaded_p (enum predication_type_index) const override + { + return false; + } + + rtx expand (function_expander &e) const override + { + e.add_input_operand (0); + return e.generate_insn (code_for_nds_vfncvt_bf16 (e.vector_mode ())); + } +}; + +static CONSTEXPR const nds_vfwcvt nds_vfwcvt_obj; +static CONSTEXPR const nds_vfncvt nds_vfncvt_obj; + +/* Declare the function base NAME, pointing it to an instance + of class _obj. */ +#define BASE(NAME) \ + namespace bases { const function_base *const NAME = &NAME##_obj; } + +BASE (nds_vfwcvt) +BASE (nds_vfncvt) + +} // end namespace riscv_vector diff --git a/gcc/config/riscv/andes-vector-builtins-bases.h b/gcc/config/riscv/andes-vector-builtins-bases.h new file mode 100644 index 000000000000..7d11761d8f6e --- /dev/null +++ b/gcc/config/riscv/andes-vector-builtins-bases.h @@ -0,0 +1,33 @@ +/* function_base declaration for Andes custom 'V' Extension for GNU compiler. + Copyright (C) 2024-2025 Free Software Foundation, Inc. + Contributed by Andes. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#ifndef GCC_ANDES_VECTOR_BUILTINS_BASES_H +#define GCC_ANDES_VECTOR_BUILTINS_BASES_H + +namespace riscv_vector { + +namespace bases { +extern const function_base *const nds_vfwcvt; +extern const function_base *const nds_vfncvt; +} + +} // end namespace riscv_vector + +#endif diff --git a/gcc/config/riscv/andes-vector-builtins-functions.def b/gcc/config/riscv/andes-vector-builtins-functions.def new file mode 100644 index 000000000000..989db8c71bab --- /dev/null +++ b/gcc/config/riscv/andes-vector-builtins-functions.def @@ -0,0 +1,45 @@ +/* Intrinsic define macros for Andes custom 'V' Extension for GNU compiler. + Copyright (C) 2024-2025 Free Software Foundation, Inc. + Contributed by Andes. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +/* Use "DEF_RVV_FUNCTION" macro to define RVV intrinsic functions. + + - NAME not only describes the base_name of the functions + but also point to the name of the function_base class. + + - SHAPE point to the function_shape class. + + - PREDS describes the predication types that are supported in the + functions. + + - OPS_INFO describes all information of return type and each + argument type. + +*/ +#ifndef DEF_RVV_FUNCTION +#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) +#endif + +/* Andes Vector Packed FP16 Extension (XAndesVBFHCvt). */ +#define REQUIRED_EXTENSIONS XANDESVBFHCVT_EXT +DEF_RVV_FUNCTION (nds_vfwcvt, alu, full_preds, bf16_to_f32_wf_v_ops) +DEF_RVV_FUNCTION (nds_vfncvt, narrow_alu, full_preds, f32_to_bf16_nf_w_ops) +#undef REQUIRED_EXTENSIONS + +#undef DEF_RVV_FUNCTION diff --git a/gcc/config/riscv/andes-vector.md b/gcc/config/riscv/andes-vector.md new file mode 100644 index 000000000000..31498ca9aab0 --- /dev/null +++ b/gcc/config/riscv/andes-vector.md @@ -0,0 +1,51 @@ +;; Machine description for Andes vendor extensions +;; Copyright (C) 2021-2025 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_c_enum "unspec" [ + UNSPEC_NDS_VFWCVTBF16 + UNSPEC_NDS_VFNCVTBF16 +]) + +;; .................... +;; +;; VECTOR BFLOAT16 CONVERSION +;; +;; .................... + +(define_insn "@nds_vfwcvt_bf16" + [(set (match_operand:NDS_VWEXTBF 0 "register_operand" "=&vr") + (unspec_volatile:NDS_VWEXTBF + [(float_extend:NDS_VWEXTBF + (match_operand: 1 "register_operand" " vr"))] + UNSPEC_NDS_VFWCVTBF16))] + "TARGET_VECTOR && TARGET_XANDESVBFHCVT" + "nds.vfwcvt.s.bf16\t%0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "")]) + +(define_insn "@nds_vfncvt_bf16" + [(set (match_operand: 0 "register_operand" "=&vr") + (unspec_volatile: + [(float_truncate: + (match_operand:NDS_VWEXTBF 1 "register_operand" " vr"))] + UNSPEC_NDS_VFNCVTBF16))] + "TARGET_VECTOR && TARGET_XANDESVBFHCVT" + "nds.vfncvt.bf16.s\t%0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "")]) diff --git a/gcc/config/riscv/andes_vector.h b/gcc/config/riscv/andes_vector.h new file mode 100644 index 000000000000..f4fb307e9bb3 --- /dev/null +++ b/gcc/config/riscv/andes_vector.h @@ -0,0 +1,32 @@ +/* Andes Vector Extension intrinsics include file. + Copyright (C) 2025 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef __ANDES_VECTOR_H +#define __ANDES_VECTOR_H + +/* TODO: This should have a separate pragma to include only the Andes + vector intrinsics. For now, we are including riscv_vector.h. */ +#include + +#endif // __ANDES_VECTOR_H diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index f652a125dc35..8f61a3a2a2ab 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -52,6 +52,7 @@ #include "riscv-vector-builtins-shapes.h" #include "riscv-vector-builtins-bases.h" #include "sifive-vector-builtins-bases.h" +#include "andes-vector-builtins-bases.h" using namespace riscv_vector; @@ -3080,6 +3081,22 @@ static CONSTEXPR const rvv_op_info all_v_scalar_ptr_index_ops rvv_arg_type_info (RVV_BASE_void), /* Return type */ scalar_ptr_index_args /* Args */}; +/* A static operand information for vector_type func (vector_type) + * function registration. */ +static CONSTEXPR const rvv_op_info f32_to_bf16_nf_w_ops + = {f32_ops, /* Types */ + OP_TYPE_bf16_s, /* Suffix */ + rvv_arg_type_info (RVV_BASE_double_trunc_bfloat_vector), /* Return type */ + v_args /* Args */}; + +/* A static operand information for vector_type func (vector_type) + * function registration. */ +static CONSTEXPR const rvv_op_info bf16_to_f32_wf_v_ops + = {f32_ops, /* Types */ + OP_TYPE_s_bf16, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + bf_w_v_args /* Args */}; + /* A static operand information for vector_type func (vector_type). Some insns just supports SEW=32, such as the crypto vector Zvkg extension. * function registration. */ @@ -3449,6 +3466,10 @@ static function_group_info function_groups[] = { #define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) \ {#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO, REQUIRED_EXTENSIONS}, #include "sifive-vector-builtins-functions.def" +#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) \ + {#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO, REQUIRED_EXTENSIONS}, +#include "andes-vector-builtins-functions.def" + }; /* The RVV types, with their built-in diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def index be3fb1af8166..c9859dc65f1b 100644 --- a/gcc/config/riscv/riscv-vector-builtins.def +++ b/gcc/config/riscv/riscv-vector-builtins.def @@ -663,6 +663,8 @@ DEF_RVV_OP_TYPE (v_vvw) DEF_RVV_OP_TYPE (v_xvw) DEF_RVV_OP_TYPE (v_ivw) DEF_RVV_OP_TYPE (v_fvw) +DEF_RVV_OP_TYPE (bf16_s) +DEF_RVV_OP_TYPE (s_bf16) DEF_RVV_PRED_TYPE (ta) DEF_RVV_PRED_TYPE (tu) diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h index 1f2587ab6afa..130ecd7eb537 100644 --- a/gcc/config/riscv/riscv-vector-builtins.h +++ b/gcc/config/riscv/riscv-vector-builtins.h @@ -131,6 +131,7 @@ enum required_ext XSFVQMACCDOD_EXT, /* XSFVQMACCDOD extension */ XSFVFNRCLIPXFQF_EXT, /* XSFVFNRCLIPXFQF extension */ XSFVCP_EXT, /* XSFVCP extension*/ + XANDESVBFHCVT_EXT, /* XANDESVBFHCVT extension */ /* Please update below to isa_name func when add or remove enum type(s). */ }; @@ -172,6 +173,8 @@ static inline const char * required_ext_to_isa_name (enum required_ext required) return "xsfvfnrclipxfqf"; case XSFVCP_EXT: return "xsfvcp"; + case XANDESVBFHCVT_EXT: + return "xandesvbfhcvt"; default: gcc_unreachable (); } @@ -217,6 +220,8 @@ static inline bool required_extensions_specified (enum required_ext required) return TARGET_XSFVFNRCLIPXFQF; case XSFVCP_EXT: return TARGET_XSFVCP; + case XANDESVBFHCVT_EXT: + return TARGET_XANDESVBFHCVT; default: gcc_unreachable (); } diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv index 0309c84e81d4..d7111cb0c06b 100644 --- a/gcc/config/riscv/t-riscv +++ b/gcc/config/riscv/t-riscv @@ -3,6 +3,7 @@ RISCV_BUILTINS_H = $(srcdir)/config/riscv/riscv-vector-builtins.h \ $(srcdir)/config/riscv/riscv-vector-builtins-functions.def \ $(srcdir)/config/riscv/thead-vector-builtins-functions.def \ $(srcdir)/config/riscv/sifive-vector-builtins-functions.def \ + $(srcdir)/config/riscv/andes-vector-builtins-functions.def \ riscv-vector-type-indexer.gen.def riscv-builtins.o: $(srcdir)/config/riscv/riscv-builtins.cc $(CONFIG_H) \ @@ -26,6 +27,7 @@ riscv-vector-builtins.o: $(srcdir)/config/riscv/riscv-vector-builtins.cc \ $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \ $(srcdir)/config/riscv/riscv-vector-builtins-bases.h \ $(srcdir)/config/riscv/sifive-vector-builtins-bases.h \ + $(srcdir)/config/riscv/andes-vector-builtins-bases.h \ $(srcdir)/config/riscv/riscv-vector-builtins-types.def \ $(srcdir)/config/riscv/sifive-vector-builtins-functions.def \ $(RISCV_BUILTINS_H) @@ -69,6 +71,19 @@ sifive-vector-builtins-bases.o: \ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/riscv/sifive-vector-builtins-bases.cc +andes-vector-builtins-bases.o: \ + $(srcdir)/config/riscv/andes-vector-builtins-bases.cc \ + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \ + $(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) $(RECOG_H) \ + $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) fold-const.h $(GIMPLE_H) \ + gimple-iterator.h gimplify.h explow.h $(EMIT_RTL_H) tree-vector-builder.h \ + rtx-vector-builder.h \ + $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \ + $(srcdir)/config/riscv/andes-vector-builtins-bases.h \ + $(RISCV_BUILTINS_H) + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/riscv/andes-vector-builtins-bases.cc + riscv-sr.o: $(srcdir)/config/riscv/riscv-sr.cc $(CONFIG_H) \ $(SYSTEM_H) $(TM_H) $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 9d5ba480fb0e..9fff335b973c 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -4929,3 +4929,16 @@ (RVVM4HI "HF") (RVVM2HI "HF") (RVVM1HI "HF") (RVVMF2HI "HF") (RVVMF4HI "HF") (RVVM4SI "SF") (RVVM2SI "SF") (RVVM1SI "SF") (RVVMF2SI "SF") ]) + +(define_mode_iterator NDS_VWEXTBF [ + (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") + (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +]) + +(define_mode_attr NDS_V_DOUBLE_TRUNC_BF [ + (RVVM8SF "RVVM4BF") (RVVM4SF "RVVM2BF") (RVVM2SF "RVVM1BF") + (RVVM1SF "RVVMF2BF") (RVVMF2SF "RVVMF4BF") +]) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 851ba4a9490a..5042365918c1 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -8703,3 +8703,4 @@ (include "autovec.md") (include "autovec-opt.md") (include "sifive-vector.md") +(include "andes-vector.md") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index d76a2d7fe74e..720cea97d77b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -43,6 +43,8 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xsfvector/*.\[cS\]]] \ "" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xtheadvector/*.\[cS\]]] \ "" $CFLAGS +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xandesvector/*.\[cS\]]] \ + "" $CFLAGS gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \ "" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/nds_vfwcvt.c b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/nds_vfwcvt.c new file mode 100644 index 000000000000..b0d2b562d548 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xandesvector/nds_vfwcvt.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gv_xandesvbfhcvt" { target { rv32 } } } */ +/* { dg-options "-march=rv64gv_xandesvbfhcvt" { target { rv64 } } } */ + +#include "andes_vector.h" + +vfloat32mf2_t +test_nds_vfwcvt_s_bf16_f32mf2 (vbfloat16mf4_t src) +{ + return __riscv_nds_vfwcvt_s_bf16_f32mf2 ((src), 0); +} + +vfloat32m1_t +test_nds_vfwcvt_s_bf16_f32m1 (vbfloat16mf2_t src) +{ + return __riscv_nds_vfwcvt_s_bf16_f32m1 ((src), 0); +} + +vfloat32m2_t +test_nds_vfwcvt_s_bf16_f32m2 (vbfloat16m1_t src) +{ + return __riscv_nds_vfwcvt_s_bf16_f32m2 ((src), 0); +} + +vfloat32m4_t +test_nds_vfwcvt_s_bf16_f32m4 (vbfloat16m2_t src) +{ + return __riscv_nds_vfwcvt_s_bf16_f32m4 ((src), 0); +} + +vfloat32m8_t +test_nds_vfwcvt_s_bf16_f32m8 (vbfloat16m4_t src) +{ + return __riscv_nds_vfwcvt_s_bf16_f32m8 ((src), 0); +} + +/* { dg-final { scan-assembler-times {nds\.vfwcvt\.s\.bf16} 5 } } */ -- 2.34.1