> Am 06.06.2025 um 17:42 schrieb Robin Dapp <rdapp....@gmail.com>:
> 
> 
>> 
>> At first I thought if we only cared about element misalignment checking the 
>> first element/pointer should be sufficient.  But riscv's gathers as well as 
>> strided loads allow byte offsets rather than element-sized offsets so there 
>> could be 16-bit loads with a stride of e.g. 1 byte.
> 
> Wait, no that doesn't make sense.  The element-alignment rule still holds 
> true so while a stride of 1 byte it would only be permissible on uarchs that 
> support element misalignment...

Note it’s far from obvious to me whether for stride and gather loads the 
alignment of the elements loaded falls under the scalar or vector load 
restriction.  Is this explicitly spelled out for risc-v or is that your 
interpretation?

Richard 

> 
> --
> Regards
> Robin
> 

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