From: Pan Li <pan2...@intel.com>
Add asm dump check test for vec_duplicate + vand.vv combine to vand.vx,
with the GR2VR cost is 0, 2 and 15.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add test cases
for vand vx combine case 0 on GR2VR cost.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
data for vand.vx run test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
.../riscv/rvv/autovec/vx_vf/vx-1-i16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-i32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-i64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-i8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-u8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-2-i16.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-2-i32.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-2-i64.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-2-i8.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-2-u8.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-3-i16.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-3-i32.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-3-i64.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-3-i8.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-3-u8.c | 4 +-
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 392 ++++++++++++++++++
.../rvv/autovec/vx_vf/vx_vand-run-1-i16.c | 15 +
.../rvv/autovec/vx_vf/vx_vand-run-1-i32.c | 15 +
.../rvv/autovec/vx_vf/vx_vand-run-1-i64.c | 15 +
.../rvv/autovec/vx_vf/vx_vand-run-1-i8.c | 15 +
.../rvv/autovec/vx_vf/vx_vand-run-1-u16.c | 15 +
.../rvv/autovec/vx_vf/vx_vand-run-1-u32.c | 15 +
.../rvv/autovec/vx_vf/vx_vand-run-1-u64.c | 15 +
.../rvv/autovec/vx_vf/vx_vand-run-1-u8.c | 15 +
33 files changed, 576 insertions(+), 16 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index 47fa654e62d..ad63a84c935 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -8,7 +8,9 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 9e16eaf5930..87d7ecbb3fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -8,7 +8,9 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index 52271bee771..4a402e5fe2c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -8,7 +8,9 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index ac822fb66c8..b30c539f310 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -8,7 +8,9 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index f4e46b7e973..fd3d726e7bd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -8,7 +8,9 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 9b83b661619..917e370cdc6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -8,7 +8,9 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index be807889d72..976a1b4687c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -8,7 +8,9 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index 5928c3f3f28..e96df13820b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -8,7 +8,9 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index 631f035d2e5..4912dbf415e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index bbef0a23ccc..1219395bf30 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index f4999fe899e..64604e228ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index 3ddfda0cfdb..e6d5e633b7b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index a4e2eb84358..35bf020705d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 87ea54d0d02..2c9d857dcbf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 990145ccc3c..ac49bffba63 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index d1495a4c486..8a3d027a57e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index 9c3102a24c0..b57d4e41b34 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index 7da01011ce7..517fc0a3ed3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 7e77db986bf..8ba77099f85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 957654fa1fe..e71127f4566 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index a62334adb4d..82d96e9289b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index d7b31e2b589..e19513ad18b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 22f55508279..62a47ec14b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index 3473c5ffc6c..d693c367c91 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -7,8 +7,10 @@
DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
-DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
+DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
+/* { dg-final { scan-assembler-not {vand.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index 08d53b28ec5..a5b4f954735 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -1182,4 +1182,396 @@ uint64_t TEST_BINARY_DATA(uint64_t, rsub)[][3][N] =
},
};
+int8_t TEST_BINARY_DATA(int8_t, and)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xff, 0xff, 0xff, 0xff,
+ },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ },
+ {
+ { 0x7f },
+ {
+ 0x7f, 0x7f, 0x7f, 0x7f,
+ 0x80, 0x80, 0x80, 0x80,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70, 0x70, 0x70, 0x70,
+ },
+ {
+ 0x7f, 0x7f, 0x7f, 0x7f,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70, 0x70, 0x70, 0x70,
+ },
+ },
+ {
+ { 0xff },
+ {
+ 0xff, 0xff, 0xff, 0xff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xff, 0xff, 0xff, 0xff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, and)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ },
+ {
+ { 0x7fff },
+ {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x8000, 0x8000, 0x8000, 0x8000,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x7000, 0x7000, 0x7000, 0x7000,
+ },
+ {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x7000, 0x7000, 0x7000, 0x7000,
+ },
+ },
+ {
+ { 0xffff },
+ {
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, and)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ },
+ {
+ { 0x7fffffff },
+ {
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+ 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70000000, 0x70000000, 0x70000000, 0x70000000,
+ },
+ {
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70000000, 0x70000000, 0x70000000, 0x70000000,
+ },
+ },
+ {
+ { 0xffffffff },
+ {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, and)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1,
0x1,
+ 0x2, 0x2, 0x2,
0x2,
+ 0x0, 0x0, 0x0,
0x0,
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ },
+ {
+ 0x1, 0x1, 0x1,
0x1,
+ 0x0, 0x0, 0x0,
0x0,
+ 0x0, 0x0, 0x0,
0x0,
+ 0x1, 0x1, 0x1,
0x1,
+ },
+ },
+ {
+ { 0x7fffffffffffffffull },
+ {
+ 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
0x7fffffffffffffffull,
+ 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
0x8000000000000000ull,
+ 0xf, 0xf, 0xf,
0xf,
+ 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
0x7000000000000000ull,
+ },
+ {
+ 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
0x7fffffffffffffffull,
+ 0x0, 0x0, 0x0,
0x0,
+ 0xf, 0xf, 0xf,
0xf,
+ 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
0x7000000000000000ull,
+ },
+ },
+ {
+ { 0xffffffffffffffffull },
+ {
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0x1f, 0x1f, 0x1f,
0x1f,
+ 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
0x8000000000000000ull,
+ 0x1, 0x1, 0x1,
0x1,
+ },
+ {
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0x1f, 0x1f, 0x1f,
0x1f,
+ 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
0x8000000000000000ull,
+ 0x1, 0x1, 0x1,
0x1,
+ },
+ },
+};
+
+uint8_t TEST_BINARY_DATA(uint8_t, and)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xff, 0xff, 0xff, 0xff,
+ },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ },
+ {
+ { 0x7f },
+ {
+ 0x7f, 0x7f, 0x7f, 0x7f,
+ 0x80, 0x80, 0x80, 0x80,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70, 0x70, 0x70, 0x70,
+ },
+ {
+ 0x7f, 0x7f, 0x7f, 0x7f,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70, 0x70, 0x70, 0x70,
+ },
+ },
+ {
+ { 0xff },
+ {
+ 0xff, 0xff, 0xff, 0xff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xff, 0xff, 0xff, 0xff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, and)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ },
+ {
+ { 0x7fff },
+ {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x8000, 0x8000, 0x8000, 0x8000,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x7000, 0x7000, 0x7000, 0x7000,
+ },
+ {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x7000, 0x7000, 0x7000, 0x7000,
+ },
+ },
+ {
+ { 0xffff },
+ {
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, and)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ },
+ {
+ { 0x7fffffff },
+ {
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+ 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70000000, 0x70000000, 0x70000000, 0x70000000,
+ },
+ {
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70000000, 0x70000000, 0x70000000, 0x70000000,
+ },
+ },
+ {
+ { 0xffffffff },
+ {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, and)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1,
0x1,
+ 0x2, 0x2, 0x2,
0x2,
+ 0x0, 0x0, 0x0,
0x0,
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ },
+ {
+ 0x1, 0x1, 0x1,
0x1,
+ 0x0, 0x0, 0x0,
0x0,
+ 0x0, 0x0, 0x0,
0x0,
+ 0x1, 0x1, 0x1,
0x1,
+ },
+ },
+ {
+ { 0x7fffffffffffffffull },
+ {
+ 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
0x7fffffffffffffffull,
+ 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
0x8000000000000000ull,
+ 0xf, 0xf, 0xf,
0xf,
+ 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
0x7000000000000000ull,
+ },
+ {
+ 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
0x7fffffffffffffffull,
+ 0x0, 0x0, 0x0,
0x0,
+ 0xf, 0xf, 0xf,
0xf,
+ 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
0x7000000000000000ull,
+ },
+ },
+ {
+ { 0xffffffffffffffffull },
+ {
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0x1f, 0x1f, 0x1f,
0x1f,
+ 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
0x8000000000000000ull,
+ 0x1, 0x1, 0x1,
0x1,
+ },
+ {
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0x1f, 0x1f, 0x1f,
0x1f,
+ 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
0x8000000000000000ull,
+ 0x1, 0x1, 0x1,
0x1,
+ },
+ },
+};
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c
new file mode 100644
index 00000000000..a6a7db80558
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int16_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c
new file mode 100644
index 00000000000..79b7569c0d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int32_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c
new file mode 100644
index 00000000000..a80d8d69068
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int64_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c
new file mode 100644
index 00000000000..d0c6f4c4e41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int8_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c
new file mode 100644
index 00000000000..44bbaec9eb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint16_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c
new file mode 100644
index 00000000000..d634a1aaf11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint32_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c
new file mode 100644
index 00000000000..10816c5ff24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint64_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c
new file mode 100644
index 00000000000..f2750161ac5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint8_t
+#define NAME and
+
+DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
--
2.43.0
