From: Pan Li <pan2...@intel.com> We have the testcase for vec_duplicate + vadd.vv combine as below already, aka:
Before: ... vmv.v.x L1: vadd.vv J L1 ... After: ... L1: vadd.vx J L1 ... But there is still another case like below: Before: ... L1: vmv.v.x vadd.vv J L1 ... After: ... L1: vadd.vx J L1 ... This patch series would like to add the testcases for this. However, some test results is not that tidy, and we need more tuning for the vector cost model. The below test suites are passed for this patch. * The rv64gcv fully regression test. Pan Li (5): RISC-V: Separate the test running of rvv vx_vf RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0 RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 0 RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 1 RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 2 .../riscv/rvv/autovec/vx_vf/vx_binary.h | 62 ++++++++++++++++--- .../riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c | 2 +- .../riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c | 9 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c | 8 +++ .../riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c | 8 +++ .../rvv/autovec/vx_vf/vx_vadd-run-1-i16.c | 4 +- .../rvv/autovec/vx_vf/vx_vadd-run-1-i32.c | 4 +- .../rvv/autovec/vx_vf/vx_vadd-run-1-i64.c | 4 +- .../rvv/autovec/vx_vf/vx_vadd-run-1-i8.c | 4 +- .../rvv/autovec/vx_vf/vx_vadd-run-1-u16.c | 4 +- .../rvv/autovec/vx_vf/vx_vadd-run-1-u32.c | 4 +- .../rvv/autovec/vx_vf/vx_vadd-run-1-u64.c | 4 +- .../rvv/autovec/vx_vf/vx_vadd-run-1-u8.c | 4 +- gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 15 +++++ 58 files changed, 301 insertions(+), 49 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c -- 2.43.0
