> On 7 May 2025, at 13:35, Richard Sandiford <richard.sandif...@arm.com> wrote:
>
> External email: Use caution opening links or attachments
>
>
> Jennifer Schmitz <jschm...@nvidia.com> writes:
>> @@ -3698,6 +3706,24 @@ aarch64_partial_ptrue_length (rtx_vector_builder
>> &builder,
>> return vl;
>> }
>>
>> +/* Return:
>> +
>> + * -1 if all bits of PRED are set
>> + * N if PRED has N leading set bits followed by all clear bits
>> + * 0 if PRED does not have any of these forms. */
>
> Sorry for the formatting nits, but the indentation looks off here.
> Each nonempty line should be indented by three spaces rather than two.
>
>> [...]
>> @@ -23526,6 +23567,39 @@ aarch64_simd_valid_imm (rtx op, simd_immediate_info
>> *info,
>> return false;
>> }
>>
>> +/* Try to optimize the expansion of a maskload or maskstore with
>> + the operands in OPERANDS, given that the vector being loaded or
>> + stored has mode MODE. Return true on success or false if the normal
>> + expansion should be used. */
>
> Same here.
>
>> +
>> +bool
>> +aarch64_expand_maskloadstore (rtx *operands, machine_mode mode)
>> +{
>> + /* If the predicate in operands[2] is a patterned SVE PTRUE predicate
>> + with patterns VL1, VL2, VL4, VL8, or VL16 and at most the bottom
>> + 128 bits are loaded/stored, emit an ASIMD load/store. */
>
> Same here (five spaces rather than three).
>
> OK with those nits fixed, thanks.
Thanks (and apologies for the formatting issues).
Pushed to trunk: 210d06502f22964c7214586c54f8eb54a6965bfd
Jennifer
>
> Richard
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