Re: [to-be-committed][RISC-V][PR target/119971] Avoid losing shift count masking

[Bernhard Reutner-Fischer]

On 5 May 2025 20:42:34 CEST, Jeff Law <jeffreya...@gmail.com> wrote:


diff --git a/gcc/testsuite/gcc.target/riscv/pr119971.c 
b/gcc/testsuite/gcc.target/riscv/pr119971.c
new file mode 100644
index 00000000000..c3f23b05ec3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr119971.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target rv64 } } */
+/* { dg-options "-march=rv64gcb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-g" "-Oz" "-Os" } } */
+


typo s/"-g"/"-Og"/ maybe?
thanks