The recent adjustment to more correctly cost register moves tripped a
few testsuite regressions.
I'm pretty torn on the thead test adjustments. But in reality they only
worked because the register move costing was broken. So I've reverted
the scan-asm part of those to a prior state for two of those tests. The
other was only failing at -Og/-Oz which was added to the exclude list.
The other Zfa test is similar, but we can make the test behave with a
suitable -mtune option and thus preserve the test.
While investigating I also noted that vector moves aren't being handled
correctly for subclasses of the integer/fp register files. So I fixed
those while I was in there.
Note this may have an impact on some of your work Pan. I haven't
followed the changes from the last week or so due to illness.
Waiting on pre-commit's verdict, though it did spin through my tester
successfully, though not all of the regressions related to that change
are addressed (there's still one for rv32 I'll look at shortly).
jeff
gcc/
* config/riscv/riscv.cc (riscv_register_move_cost): Handle
subclasses with vector registers as well.
gcc/testsuite/
* gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust expected
output.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise.
* gcc.target/riscv/xtheadfmv-fmv.c: Skip for -Os and -Oz.
* gcc.target/riscv/zfa-fmovh-fmovp.c: Use sifive-p400 tuning.
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ed635ab42f4..9f13eeedea8 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9659,17 +9659,17 @@ riscv_register_move_cost (machine_mode mode,
if (from == V_REGS)
{
- if (to == GR_REGS)
+ if (to_is_gpr)
return get_vector_costs ()->regmove->VR2GR;
- else if (to == FP_REGS)
+ else if (to_is_fpr)
return get_vector_costs ()->regmove->VR2FR;
}
if (to == V_REGS)
{
- if (from == GR_REGS)
+ if (from_is_gpr)
return get_vector_costs ()->regmove->GR2VR;
- else if (from == FP_REGS)
+ else if (from_is_fpr)
return get_vector_costs ()->regmove->FR2VR;
}
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
index 6746c314057..38966fefad5 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
index fb1ac2b735c..f0d9c80d16f 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c
@@ -35,6 +35,4 @@ double foo (int i, int j)
return z;
}
-/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */
-/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
index 5a52adce36a..150cfd7fc05 100644
--- a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
+++ b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32g_zfa -mabi=ilp32 -O0" } */
+/* { dg-options "-march=rv32g_zfa -mabi=ilp32 -O0 -mtune=sifive-p400-series" }
*/
double foo(long long a)
{
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
index 9b4e2378448..81b240eac57 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { rv32 } } } */
/* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */
double
ll2d (long long ll)
