Wilco Dijkstra <wilco.dijks...@arm.com> writes:
> Update FMV features to latest ACLE spec of 2024Q4 - several features have
> been removed
> or merged. Add FMV support for CSSC and MOPS. Preserve the ordering in enum
> CPUFeatures.
>
> gcc:
> * common/config/aarch64/cpuinfo.h: Remove unused features, add
> FEAT_CSSC
> and FEAT_MOPS.
> * config/aarch64/aarch64-option-extensions.def: Remove FMV support
> for RPRES, use PULL rather than AES, add FMV support for CSSC and
> MOPS.
>
> libgcc:
> * config/aarch64/cpuinfo.c (__init_cpu_features_constructor):
> Remove unused features, add support for CSSC and MOPS.
OK, thanks.
Not your fault, but I was initially confused that, when two
architectural features are combined into a single FMV feature, the
FEAT_* macro names followed the "more specific" architectural feature,
whereas the user-visible FMV feature names followed the "least specific"
architectural feature. E.g. architectural FEAT_SBBS + FEAT_SBBS2 is
represented by the macro FEAT_SBBS2 and the feature string "sbbs".
Similarly FEAT_AES + FEAT_PMULL is represented by the macro FEAT_PMULL
and the feature string "aes". But I can see why the macro naming
makes sense in the context of hwcaps checks, and in any case we should
maintain compatibility with compiler-rt rather than pick our own naming.
Richard
>
> ---
>
> diff --git a/gcc/common/config/aarch64/cpuinfo.h
> b/gcc/common/config/aarch64/cpuinfo.h
> index
> cd3c2b20c5315b035870528fa39246bbc780f369..d329d861bf73fbb03436643d09553d7eabecdfb8
> 100644
> --- a/gcc/common/config/aarch64/cpuinfo.h
> +++ b/gcc/common/config/aarch64/cpuinfo.h
> @@ -39,10 +39,10 @@ enum CPUFeatures {
> FEAT_FP,
> FEAT_SIMD,
> FEAT_CRC,
> - FEAT_SHA1,
> + FEAT_CSSC,
> FEAT_SHA2,
> FEAT_SHA3,
> - FEAT_AES,
> + FEAT_unused5,
> FEAT_PMULL,
> FEAT_FP16,
> FEAT_DIT,
> @@ -53,30 +53,30 @@ enum CPUFeatures {
> FEAT_RCPC,
> FEAT_RCPC2,
> FEAT_FRINTTS,
> - FEAT_DGH,
> + FEAT_unused6,
> FEAT_I8MM,
> FEAT_BF16,
> - FEAT_EBF16,
> - FEAT_RPRES,
> + FEAT_unused7,
> + FEAT_unused8,
> FEAT_SVE,
> - FEAT_SVE_BF16,
> - FEAT_SVE_EBF16,
> - FEAT_SVE_I8MM,
> + FEAT_unused9,
> + FEAT_unused10,
> + FEAT_unused11,
> FEAT_SVE_F32MM,
> FEAT_SVE_F64MM,
> FEAT_SVE2,
> - FEAT_SVE_AES,
> + FEAT_unused12,
> FEAT_SVE_PMULL128,
> FEAT_SVE_BITPERM,
> FEAT_SVE_SHA3,
> FEAT_SVE_SM4,
> FEAT_SME,
> - FEAT_MEMTAG,
> + FEAT_unused13,
> FEAT_MEMTAG2,
> - FEAT_MEMTAG3,
> + FEAT_unused14,
> FEAT_SB,
> FEAT_unused1,
> - FEAT_SSBS,
> + FEAT_unused15,
> FEAT_SSBS2,
> FEAT_BTI,
> FEAT_unused2,
> @@ -87,6 +87,7 @@ enum CPUFeatures {
> FEAT_SME_I64,
> FEAT_SME2,
> FEAT_RCPC3,
> + FEAT_MOPS,
> FEAT_MAX,
> FEAT_EXT = 62, /* Reserved to indicate presence of additional features
> field
> in __aarch64_cpu_features. */
> diff --git a/gcc/config/aarch64/aarch64-option-extensions.def
> b/gcc/config/aarch64/aarch64-option-extensions.def
> index
> 79b79358c5d4a9e23c7601f7a1ba742dddadb778..b111b33d9bc75c8b85faf672fba051e0e417b796
> 100644
> --- a/gcc/config/aarch64/aarch64-option-extensions.def
> +++ b/gcc/config/aarch64/aarch64-option-extensions.def
> @@ -128,7 +128,9 @@ AARCH64_OPT_FMV_EXTENSION("sha2", SHA2, (SIMD), (), (),
> "sha1 sha2")
>
> AARCH64_FMV_FEATURE("sha3", SHA3, (SHA3))
>
> -AARCH64_OPT_FMV_EXTENSION("aes", AES, (SIMD), (), (), "aes")
> +AARCH64_OPT_EXTENSION("aes", AES, (SIMD), (), (), "aes")
> +
> +AARCH64_FMV_FEATURE("aes", PMULL, (AES))
>
> /* +nocrypto disables AES, SHA2 and SM4, and anything that depends on them
> (such as SHA3 and the SVE2 crypto extensions). */
> @@ -171,8 +173,6 @@ AARCH64_OPT_FMV_EXTENSION("i8mm", I8MM, (SIMD), (), (),
> "i8mm")
> instructions. */
> AARCH64_OPT_FMV_EXTENSION("bf16", BF16, (FP), (SIMD), (), "bf16")
>
> -AARCH64_FMV_FEATURE("rpres", RPRES, ())
> -
> AARCH64_OPT_FMV_EXTENSION("sve", SVE, (SIMD, F16, FCMA), (), (), "sve")
>
> /* This specifically does not imply +sve. */
> @@ -190,7 +190,7 @@ AARCH64_OPT_FMV_EXTENSION("sve2", SVE2, (SVE), (), (),
> "sve2")
>
> AARCH64_OPT_EXTENSION("sve2-aes", SVE2_AES, (SVE2, AES), (), (), "sveaes")
>
> -AARCH64_FMV_FEATURE("sve2-aes", SVE_AES, (SVE2_AES))
> +AARCH64_FMV_FEATURE("sve2-aes", SVE_PMULL128, (SVE2_AES))
>
> AARCH64_OPT_EXTENSION("sve2-bitperm", SVE2_BITPERM, (SVE2), (), (),
> "svebitperm")
> @@ -245,9 +245,9 @@ AARCH64_OPT_EXTENSION("sme-b16b16", SME_B16B16, (SME2,
> SVE_B16B16), (), (), "sme
>
> AARCH64_OPT_EXTENSION("sme-f16f16", SME_F16F16, (SME2), (), (), "smef16f16")
>
> -AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "mops")
> +AARCH64_OPT_FMV_EXTENSION("mops", MOPS, (), (), (), "mops")
>
> -AARCH64_OPT_EXTENSION("cssc", CSSC, (), (), (), "cssc")
> +AARCH64_OPT_FMV_EXTENSION("cssc", CSSC, (), (), (), "cssc")
>
> AARCH64_OPT_EXTENSION("lse128", LSE128, (LSE), (), (), "lse128")
>
> diff --git a/libgcc/config/aarch64/cpuinfo.c b/libgcc/config/aarch64/cpuinfo.c
> index
> dda9dc696893cd392dd1e15d03672053cc481c6f..14877f5d8410a51fe47f94cb1a2ff5399f95c253
> 100644
> --- a/libgcc/config/aarch64/cpuinfo.c
> +++ b/libgcc/config/aarch64/cpuinfo.c
> @@ -230,9 +230,15 @@ struct {
> #ifndef HWCAP2_SVE_EBF16
> #define HWCAP2_SVE_EBF16 (1UL << 33)
> #endif
> +#ifndef HWCAP2_CSSC
> +#define HWCAP2_CSSC (1UL << 34)
> +#endif
> #ifndef HWCAP2_SME2
> #define HWCAP2_SME2 (1UL << 37)
> #endif
> +#ifndef HWCAP2_MOPS
> +#define HWCAP2_MOPS (1UL << 43)
> +#endif
> #ifndef HWCAP2_LRCPC3
> #define HWCAP2_LRCPC3 (1UL << 46)
> #endif
> @@ -269,10 +275,6 @@ __init_cpu_features_constructor (unsigned long hwcap,
> setCPUFeature(FEAT_DIT);
> if (hwcap & HWCAP_ASIMDRDM)
> setCPUFeature(FEAT_RDM);
> - if (hwcap & HWCAP_AES)
> - setCPUFeature(FEAT_AES);
> - if (hwcap & HWCAP_SHA1)
> - setCPUFeature(FEAT_SHA1);
> if (hwcap & HWCAP_SHA2)
> setCPUFeature(FEAT_SHA2);
> if (hwcap & HWCAP_JSCVT)
> @@ -282,19 +284,9 @@ __init_cpu_features_constructor (unsigned long hwcap,
> if (hwcap & HWCAP_SB)
> setCPUFeature(FEAT_SB);
> if (hwcap & HWCAP_SSBS)
> - {
> - setCPUFeature(FEAT_SSBS);
> - setCPUFeature(FEAT_SSBS2);
> - }
> + setCPUFeature(FEAT_SSBS2);
> if (hwcap2 & HWCAP2_MTE)
> - {
> - setCPUFeature(FEAT_MEMTAG);
> - setCPUFeature(FEAT_MEMTAG2);
> - }
> - if (hwcap2 & HWCAP2_MTE3)
> - setCPUFeature(FEAT_MEMTAG3);
> - if (hwcap2 & HWCAP2_SVEAES)
> - setCPUFeature(FEAT_SVE_AES);
> + setCPUFeature(FEAT_MEMTAG2);
> if (hwcap2 & HWCAP2_SVEPMULL)
> setCPUFeature(FEAT_SVE_PMULL128);
> if (hwcap2 & HWCAP2_SVEBITPERM)
> @@ -311,24 +303,14 @@ __init_cpu_features_constructor (unsigned long hwcap,
> setCPUFeature(FEAT_RNG);
> if (hwcap2 & HWCAP2_I8MM)
> setCPUFeature(FEAT_I8MM);
> - if (hwcap2 & HWCAP2_EBF16)
> - setCPUFeature(FEAT_EBF16);
> - if (hwcap2 & HWCAP2_SVE_EBF16)
> - setCPUFeature(FEAT_SVE_EBF16);
> - if (hwcap2 & HWCAP2_DGH)
> - setCPUFeature(FEAT_DGH);
> if (hwcap2 & HWCAP2_FRINT)
> setCPUFeature(FEAT_FRINTTS);
> - if (hwcap2 & HWCAP2_SVEI8MM)
> - setCPUFeature(FEAT_SVE_I8MM);
> if (hwcap2 & HWCAP2_SVEF32MM)
> setCPUFeature(FEAT_SVE_F32MM);
> if (hwcap2 & HWCAP2_SVEF64MM)
> setCPUFeature(FEAT_SVE_F64MM);
> if (hwcap2 & HWCAP2_BTI)
> setCPUFeature(FEAT_BTI);
> - if (hwcap2 & HWCAP2_RPRES)
> - setCPUFeature(FEAT_RPRES);
> if (hwcap2 & HWCAP2_WFXT)
> setCPUFeature(FEAT_WFXT);
> if (hwcap2 & HWCAP2_SME)
> @@ -339,6 +321,10 @@ __init_cpu_features_constructor (unsigned long hwcap,
> setCPUFeature(FEAT_SME_I64);
> if (hwcap2 & HWCAP2_SME_F64F64)
> setCPUFeature(FEAT_SME_F64);
> + if (hwcap2 & HWCAP2_MOPS)
> + setCPUFeature(FEAT_MOPS);
> + if (hwcap2 & HWCAP2_CSSC)
> + setCPUFeature(FEAT_CSSC);
> if (hwcap & HWCAP_FP)
> {
> setCPUFeature(FEAT_FP);
> @@ -355,8 +341,6 @@ __init_cpu_features_constructor (unsigned long hwcap,
> setCPUFeature(FEAT_RCPC3);
> if (hwcap2 & HWCAP2_BF16)
> setCPUFeature(FEAT_BF16);
> - if (hwcap2 & HWCAP2_SVEBF16)
> - setCPUFeature(FEAT_SVE_BF16);
> if (hwcap & HWCAP_SVE)
> setCPUFeature(FEAT_SVE);
> if (hwcap2 & HWCAP2_SVE2)
