On Fri, Apr 25, 2025 at 8:53 PM Jeff Law <jeffreya...@gmail.com> wrote: > > > > On 4/25/25 9:25 PM, Andrew Pinski wrote: > > This adds the simplification of a ZERO_EXTEND of an AND. This optimization > > was already handled in combine via combine_simplify_rtx and the handling > > there of compound_operations (ZERO_EXTRACT). > > > > Build and tested for aarch64-linux-gnu. > > Bootstrapped and tested on x86_64-linux-gnu. > > > > gcc/ChangeLog: > > > > * simplify-rtx.cc (simplify_context::simplify_unary_operation_1) > > <case ZERO_EXTEND>: > > Add simplifcation for and with a constant. > Funny. That might allow simplification of a patch Shreya and I were > about to submit. > > On the RISC-V port we do not define SHIFT_COUNT_TRUNCATED so if we want > to eliminate any explicit masking of the shift count/bit position we > need patterns which incorporate the masking operation. > > While putting those together recently we found that we often had an > extraneous zero_extend. That was the last technical question on that > patchkit. > > OK for the trunk.
Thanks for the approval. I had forgot mention where I noticed this. It was when I was looking into gcc.target/aarch64/ccmp_3.c failure (That got fixed a different way), https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118755#c2. That is it shows up when dealing with booleans on aarch64. It was unrelated to shifts though I have seen a similar issue with zero_extend with shifts recently too but I can't remember where. Thanks, Andrew Pinski > > jeff >
