Hi Tejas,
> On 14 Apr 2025, at 16:04, Tejas Belagod <tejas.bela...@arm.com> wrote:
>
> The operand order to gen_vcond_mask call in the vec_extract pattern is wrong.
> Fix the order where predicate is operand 3.
>
> Tested and bootstrapped on aarch64-linux-gnu. OK for trunk?
>
> gcc/ChangeLog
>
> * config/aarch64/aarch64-sve.md (vec_extract<vpred><Vel>): Fix operand
> order to gen_vcond_mask_*.
> ---
> gcc/config/aarch64/aarch64-sve.md | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64-sve.md
> b/gcc/config/aarch64/aarch64-sve.md
> index 3dbd65986ec..d4af3706294 100644
> --- a/gcc/config/aarch64/aarch64-sve.md
> +++ b/gcc/config/aarch64/aarch64-sve.md
> @@ -3133,9 +3133,9 @@
> "TARGET_SVE"
> {
> rtx tmp = gen_reg_rtx (<MODE>mode);
> - emit_insn (gen_vcond_mask_<mode><vpred> (tmp, operands[1],
> - CONST1_RTX (<MODE>mode),
> - CONST0_RTX (<MODE>mode)));
> + emit_insn (gen_vcond_mask_<mode><vpred> (tmp, CONST1_RTX (<MODE>mode),
> + CONST0_RTX (<MODE>mode),
> + operands[1]));
> emit_insn (gen_vec_extract<mode><Vel> (operands[0], tmp, operands[2]));
> DONE;
Looks like a correct fix, is there a test case where this causes a problem?
Does it need back porting?
Thanks,
Kyrill
> }
> --
> 2.25.1
>
