Apple Rosetta 2 x86-64 emulator is known to not support SAHF
instruction, which otherwise might be generated when targetting
-march=x86-64-v2.
PR target/119781
gcc/ChangeLog:
* doc/invoke.texi: Document lack of SAHF on Apple Rosetta 2.
Signed-off-by: Dimitri John Ledkov <dimitri.led...@surgut.co.uk>
---
gcc/doc/invoke.texi | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 67155eeeda7..0efcef0957b 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -36226,6 +36226,7 @@ Early Intel Pentium 4 CPUs with Intel 64 support,
prior to the introduction of Pentium 4 G1 step in December 2005,
lacked the @code{LAHF} and @code{SAHF} instructions
which are supported by AMD64.
+Apple Rosetta 2 x86-64 emulator is also known to not support this instruction.
These are load and store instructions, respectively, for certain status flags.
In 64-bit mode, the @code{SAHF} instruction is used to optimize @code{fmod},
@code{drem}, and @code{remainder} built-in functions;
--
2.43.0
