Trivial fallout from the recent combine work. We end up with a srai
rather than an xor in some of the saturation sequences. Both variants
look equally performant, so I'm just adjusting the expected test output.
Pushing to the trunk.
Jeff
commit c08d717ce9e18dcfa5b4efe49a5f570ac32fd1cf
Author: Jeff Law <j...@ventanamicro.com>
Date: Wed Apr 2 14:30:34 2025 -0600
Revert "RISC-V: Make VXRM as global register [PR118103]"
This reverts commit 1c8e6734d2dd3a6236d94c6e4e0c6780f35ede9f.
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 38f3ae7cd84..36a210f02fc 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -10914,9 +10914,7 @@ riscv_conditional_register_usage (void)
call_used_regs[regno] = 1;
}
- if (TARGET_VECTOR)
- global_regs[VXRM_REGNUM] = 1;
- else
+ if (!TARGET_VECTOR)
{
for (int regno = V_REG_FIRST; regno <= V_REG_LAST; regno++)
fixed_regs[regno] = call_used_regs[regno] = 1;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118103-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118103-2.c
deleted file mode 100644
index d6e3aa09077..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118103-2.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-#define N 4
-uint16_t a[N];
-uint16_t b[N];
-uint16_t c[N];
-
-void initialize ()
-{
- uint16_t tmp_0[N] = { 0xfff, 3213, 238, 275, };
-
- for (int i = 0; i < N; ++i)
- a[i] = b[i] = tmp_0[i];
-
- for (int i = 0; i < N; ++i)
- c[i] = 0;
-}
-
-void compute ()
-{
- size_t vl = __riscv_vsetvl_e16m1 (N);
- vuint16m1_t va = __riscv_vle16_v_u16m1 (a, vl);
- vuint16m1_t vb = __riscv_vle16_v_u16m1 (b, vl);
- vuint16m1_t vc = __riscv_vaaddu_vv_u16m1 (va, vb, __RISCV_VXRM_RDN, vl);
-
- __riscv_vse16_v_u16m1 (c, vc, vl);
-}
-
-int main ()
-{
- initialize ();
- compute();
-
- return 0;
-}
-
-/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*[01234]} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118103-run-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118103-run-2.c
deleted file mode 100644
index 89150d4f6b5..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118103-run-2.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3" } */
-
-#include "riscv_vector.h"
-
-#define N 4
-uint16_t a[N];
-uint16_t b[N];
-uint16_t c[N];
-
-void initialize () {
- uint16_t tmp_0[N] = { 0xfff, 3213, 238, 275, };
- uint16_t tmp_1[N] = { 0x2, 823, 39, 9, };
-
- for (int i = 0; i < N; ++i)
- {
- a[i] = tmp_0[i];
- b[i] = tmp_1[i];
- }
-
- for (int i = 0; i < N; ++i)
- c[i] = 0;
-}
-
-void compute ()
-{
- size_t vl = __riscv_vsetvl_e16m1 (N);
- vuint16m1_t va = __riscv_vle16_v_u16m1 (a, vl);
- vuint16m1_t vb = __riscv_vle16_v_u16m1 (b, vl);
- vuint16m1_t vc = __riscv_vaaddu_vv_u16m1 (va, vb, __RISCV_VXRM_RDN, vl);
-
- __riscv_vse16_v_u16m1 (c, vc, vl);
-}
-
-int main ()
-{
- initialize ();
- compute ();
-
- if (c[0] != 2048)
- __builtin_abort ();
-
- return 0;
-}
