The new SVE tests didn't explicitly force SVE to be enabled,
which meant that they wouldn't work on targets that aren't
configured for SVE by default.  The least invasive way of
fixing that is to add a pragma, which works for most tests.
However, for udr-sve.c, the global:

 #pragma omp declare reduction (+:svint32_t: omp_out = svadd_s32_z 
(svptrue_b32(), omp_in, omp_out)) \
                    initializer (omp_priv = svindex_s32 (0, 0))

does not work with an earlier:

 #pragma GCC target "+sve"

which is interesting, and maybe worthy of a PR if there isn't one
already.  It seems we have to force SVE (and thus an architecture)
on the command line instead.

However, with that fixed, udr-sve.c fails execution.  One problem
seems to be a missing accumulation in for_reduction.  Fixing that
is enough to reach the final inscan_reduction_incl, but that fails
for reasons I haven't investigated yet.  I would need to read up
more to understand what the loop is doing.

It also looks like there might be a missing "+" in simd_reduction:

  #pragma omp simd reduction (+:va, i)
  for (j = 0; j < 16; j++)
    va = svld1_s32 (svptrue_b32 (), a);

  res = svaddv_s32 (svptrue_b32 (), va);

  if (res != 8)
    __builtin_abort ();

since AFAICT the loop is not doing a reduction as things stand.
But perhaps that's deliberate, since it does match the != 8 test.

Tested on aarch64-linux-gnu, where it fixes everything apart from
the udr-sve.c execution failure.  Should I install this as a partial
fix, or would you prefer to fix everything in one go?

Richard


libgomp/
        * testsuite/libgomp.c-target/aarch64/firstprivate.c: Add +sve pragma.
        * testsuite/libgomp.c-target/aarch64/lastprivate.c: Likewise.
        * testsuite/libgomp.c-target/aarch64/private.c: Likewise.
        * testsuite/libgomp.c-target/aarch64/shared.c: Likewise.
        * testsuite/libgomp.c-target/aarch64/simd-aligned.c: Likewise.
        * testsuite/libgomp.c-target/aarch64/simd-nontemporal.c: Likewise.
        * testsuite/libgomp.c-target/aarch64/threadprivate.c: Likewise.
        * testsuite/libgomp.c-target/aarch64/udr-sve.c: Add an -march option.
        (for_reduction): Use "+=" in the reduction loop.
---
 libgomp/testsuite/libgomp.c-target/aarch64/firstprivate.c     | 2 ++
 libgomp/testsuite/libgomp.c-target/aarch64/lastprivate.c      | 2 ++
 libgomp/testsuite/libgomp.c-target/aarch64/private.c          | 2 ++
 libgomp/testsuite/libgomp.c-target/aarch64/shared.c           | 2 ++
 libgomp/testsuite/libgomp.c-target/aarch64/simd-aligned.c     | 2 ++
 libgomp/testsuite/libgomp.c-target/aarch64/simd-nontemporal.c | 2 ++
 libgomp/testsuite/libgomp.c-target/aarch64/threadprivate.c    | 2 ++
 libgomp/testsuite/libgomp.c-target/aarch64/udr-sve.c          | 4 ++--
 8 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/libgomp/testsuite/libgomp.c-target/aarch64/firstprivate.c 
b/libgomp/testsuite/libgomp.c-target/aarch64/firstprivate.c
index 930ca6215b6..58674e23dbb 100644
--- a/libgomp/testsuite/libgomp.c-target/aarch64/firstprivate.c
+++ b/libgomp/testsuite/libgomp.c-target/aarch64/firstprivate.c
@@ -1,6 +1,8 @@
 /* { dg-do run { target aarch64_sve256_hw } } */
 /* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */
 
+#pragma GCC target "+sve"
+
 #include <arm_sve.h>
 #include <omp.h>
 
diff --git a/libgomp/testsuite/libgomp.c-target/aarch64/lastprivate.c 
b/libgomp/testsuite/libgomp.c-target/aarch64/lastprivate.c
index be5a618c1b8..2f93d7bb312 100644
--- a/libgomp/testsuite/libgomp.c-target/aarch64/lastprivate.c
+++ b/libgomp/testsuite/libgomp.c-target/aarch64/lastprivate.c
@@ -1,6 +1,8 @@
 /* { dg-do run { target aarch64_sve256_hw } } */
 /* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */
 
+#pragma GCC target "+sve"
+
 #include <arm_sve.h>
 #include <omp.h>
 
diff --git a/libgomp/testsuite/libgomp.c-target/aarch64/private.c 
b/libgomp/testsuite/libgomp.c-target/aarch64/private.c
index 0ca74fe4e4b..fed5370c8d0 100644
--- a/libgomp/testsuite/libgomp.c-target/aarch64/private.c
+++ b/libgomp/testsuite/libgomp.c-target/aarch64/private.c
@@ -1,6 +1,8 @@
 /* { dg-do run { target aarch64_sve256_hw } } */
 /* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */
 
+#pragma GCC target "+sve"
+
 #include <arm_sve.h>
 #include <omp.h>
 
diff --git a/libgomp/testsuite/libgomp.c-target/aarch64/shared.c 
b/libgomp/testsuite/libgomp.c-target/aarch64/shared.c
index dec41b80038..340a668c0f3 100644
--- a/libgomp/testsuite/libgomp.c-target/aarch64/shared.c
+++ b/libgomp/testsuite/libgomp.c-target/aarch64/shared.c
@@ -1,6 +1,8 @@
 /* { dg-do run { target aarch64_sve256_hw } } */
 /* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */
 
+#pragma GCC target "+sve"
+
 #include <arm_sve.h>
 #include <stdlib.h>
 #include <omp.h>
diff --git a/libgomp/testsuite/libgomp.c-target/aarch64/simd-aligned.c 
b/libgomp/testsuite/libgomp.c-target/aarch64/simd-aligned.c
index cc41139a6cb..14642c975c5 100644
--- a/libgomp/testsuite/libgomp.c-target/aarch64/simd-aligned.c
+++ b/libgomp/testsuite/libgomp.c-target/aarch64/simd-aligned.c
@@ -1,6 +1,8 @@
 /* { dg-do run { target aarch64_sve256_hw } } */
 /* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */
 
+#pragma GCC target "+sve"
+
 #include <arm_sve.h>
 #include <stdint.h>
 
diff --git a/libgomp/testsuite/libgomp.c-target/aarch64/simd-nontemporal.c 
b/libgomp/testsuite/libgomp.c-target/aarch64/simd-nontemporal.c
index 3385427f364..6fe4616490a 100644
--- a/libgomp/testsuite/libgomp.c-target/aarch64/simd-nontemporal.c
+++ b/libgomp/testsuite/libgomp.c-target/aarch64/simd-nontemporal.c
@@ -1,6 +1,8 @@
 /* { dg-do run { target aarch64_sve256_hw } } */
 /* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */
 
+#pragma GCC target "+sve"
+
 #include <arm_sve.h>
 #include <stdint.h>
 
diff --git a/libgomp/testsuite/libgomp.c-target/aarch64/threadprivate.c 
b/libgomp/testsuite/libgomp.c-target/aarch64/threadprivate.c
index 4a3931210f0..aa7d2f96223 100644
--- a/libgomp/testsuite/libgomp.c-target/aarch64/threadprivate.c
+++ b/libgomp/testsuite/libgomp.c-target/aarch64/threadprivate.c
@@ -1,6 +1,8 @@
 /* { dg-do run { target aarch64_sve256_hw } } */
 /* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */
 
+#pragma GCC target "+sve"
+
 #include <arm_sve.h>
 #include <stdint.h>
 
diff --git a/libgomp/testsuite/libgomp.c-target/aarch64/udr-sve.c 
b/libgomp/testsuite/libgomp.c-target/aarch64/udr-sve.c
index c79f4a9143f..03d93cc44b2 100644
--- a/libgomp/testsuite/libgomp.c-target/aarch64/udr-sve.c
+++ b/libgomp/testsuite/libgomp.c-target/aarch64/udr-sve.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target aarch64_sve256_hw } } */
-/* { dg-options "-msve-vector-bits=256 -fopenmp -O2" } */
+/* { dg-options "-march=armv8-a+sve -msve-vector-bits=256 -fopenmp -O2" } */
 
 #include <arm_sve.h>
 
@@ -38,7 +38,7 @@ for_reduction ()
 
   #pragma omp parallel for reduction (+:va)
   for (j = 0; j < 8; j++)
-    va = svld1_s32 (svptrue_b32 (), a);
+    va += svld1_s32 (svptrue_b32 (), a);
 
   res = svaddv_s32 (svptrue_b32 (), va);
 
-- 
2.43.0

Reply via email to