[PATCH] i386: Add attr_isa for vaes patterns to sync with attr gpr16. [pr119473]

[Hu, Lin1]

For vaes patterns with jm constraint and gpr16 attr, it requires "isa"
attr to distinct avx/avx512 alternatives in ix86_memory_address_reg_class.
Also adds missing type and mode attributes for those vaes patterns.

gcc/ChangeLog:

        PR target/119473
        * config/i386/sse.md
        (vaesdec_<mode>): Set attr "isa" as "avx,vaes_avx512vl", "type" as
        "sselog1", "mode" as "TI".
        (vaesdeclast_<mode>): Ditto.
        (vaesenc_<mode>): Ditto.
        (vaesenclast_<mode>): Ditto.

gcc/testsuite/ChangeLog:

        PR target/119473
        * gcc.target/i386/pr119473.c: New test.

Co-authored-by: Hongyu Wang <hongyu.w...@intel.com>
---
 gcc/config/i386/sse.md                   | 20 +++++++++++++++----
 gcc/testsuite/gcc.target/i386/pr119473.c | 25 ++++++++++++++++++++++++
 2 files changed, 41 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr119473.c

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index ed5ac1abe80..538a7f7bdd5 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -30845,7 +30845,10 @@ (define_insn "vaesdec_<mode>"
   else
     return "vaesdec\t{%2, %1, %0|%0, %1, %2}";
 }
-[(set_attr "addr" "gpr16,*")])
+[(set_attr "isa" "avx,vaes_avx512vl")
+ (set_attr "type" "sselog1")
+ (set_attr "addr" "gpr16,*")
+ (set_attr "mode" "TI")])
 
 (define_insn "vaesdeclast_<mode>"
   [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=x,v")
@@ -30860,7 +30863,10 @@ (define_insn "vaesdeclast_<mode>"
   else
     return "vaesdeclast\t{%2, %1, %0|%0, %1, %2}";
 }
-[(set_attr "addr" "gpr16,*")])
+[(set_attr "isa" "avx,vaes_avx512vl")
+ (set_attr "type" "sselog1")
+ (set_attr "addr" "gpr16,*")
+ (set_attr "mode" "TI")])
 
 (define_insn "vaesenc_<mode>"
   [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=x,v")
@@ -30875,7 +30881,10 @@ (define_insn "vaesenc_<mode>"
   else
     return "vaesenc\t{%2, %1, %0|%0, %1, %2}";
 }
-[(set_attr "addr" "gpr16,*")])
+[(set_attr "isa" "avx,vaes_avx512vl")
+ (set_attr "type" "sselog1")
+ (set_attr "addr" "gpr16,*")
+ (set_attr "mode" "TI")])
 
 (define_insn "vaesenclast_<mode>"
   [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=x,v")
@@ -30890,7 +30899,10 @@ (define_insn "vaesenclast_<mode>"
   else
     return "vaesenclast\t{%2, %1, %0|%0, %1, %2}";
 }
-[(set_attr "addr" "gpr16,*")])
+[(set_attr "isa" "avx,vaes_avx512vl")
+ (set_attr "type" "sselog1")
+ (set_attr "addr" "gpr16,*")
+ (set_attr "mode" "TI")])
 
 (define_insn "vpclmulqdq_<mode>"
   [(set (match_operand:VI8_FVL 0 "register_operand" "=v")
diff --git a/gcc/testsuite/gcc.target/i386/pr119473.c 
b/gcc/testsuite/gcc.target/i386/pr119473.c
new file mode 100644
index 00000000000..62287c5c3b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr119473.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mapxf -m64 -mvaes" } */
+
+typedef char __v32qi __attribute__ ((__vector_size__(32)));
+typedef long long __m256i __attribute__((__vector_size__(32), 
__aligned__(32)));
+
+typedef union
+{
+  __v32qi qi[8];
+} tmp_u;
+
+
+void foo ()
+{
+  register tmp_u *tdst __asm__("%rdx");
+  register tmp_u *src1 __asm__("%rcx");
+  register tmp_u *src2 __asm__("%r26");
+
+  tdst->qi[0] = __builtin_ia32_vaesdec_v32qi(src1->qi[0], src2->qi[0]);
+  tdst->qi[0] = __builtin_ia32_vaesdeclast_v32qi(src1->qi[0], src2->qi[0]);
+  tdst->qi[0] = __builtin_ia32_vaesenc_v32qi(src1->qi[0], src2->qi[0]);
+  tdst->qi[0] = __builtin_ia32_vaesenclast_v32qi(src1->qi[0], src2->qi[0]);
+}
+
+/* { dg-final { scan-assembler-not "\\\(%r26\\\), " } } */
-- 
2.31.1