On Tue, 25 Mar 2025, Richard Biener wrote: > The following resolves missing reservations for DFmode *movdf_internal > loads and stores, visible as 'nothing' in -fsched-verbose=2 dumps. > > Bootstrap and regtest running on x86_64-unknown-linux-gnu.
The alternative for the larger scale problem of missing DFmode handling is to s/V1DF/DF/ in the file - znver.md gets along without V1DF handling, supposedly using V1DF (V1SF isn't a thing) was a mistake? Richard. > PR target/119010 > * config/i386/zn4zn5.md (znver4_sse_mov_fp, znver4_sse_mov_fp_load, > znver5_sse_mov_fp_load, znver4_sse_mov_fp_store, > znver5_sse_mov_fp_store): Also match V1SF and DF. > --- > gcc/config/i386/zn4zn5.md | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/gcc/config/i386/zn4zn5.md b/gcc/config/i386/zn4zn5.md > index ae188a1201e..f8772fed620 100644 > --- a/gcc/config/i386/zn4zn5.md > +++ b/gcc/config/i386/zn4zn5.md > @@ -986,35 +986,35 @@ > (define_insn_reservation "znver4_sse_mov_fp" 1 > (and (eq_attr "cpu" "znver4,znver5") > (and (eq_attr "type" "ssemov") > - (and (eq_attr "mode" > "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") > + (and (eq_attr "mode" > "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF") > (eq_attr "memory" "none")))) > "znver4-direct,znver4-fpu") > > (define_insn_reservation "znver4_sse_mov_fp_load" 6 > (and (eq_attr "cpu" "znver4") > (and (eq_attr "type" "ssemov") > - (and (eq_attr "mode" > "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") > + (and (eq_attr "mode" > "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF") > (eq_attr "memory" "load")))) > "znver4-direct,znver4-load,znver4-fpu") > > (define_insn_reservation "znver5_sse_mov_fp_load" 6 > (and (eq_attr "cpu" "znver5") > (and (eq_attr "type" "ssemov") > - (and (eq_attr "mode" > "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") > + (and (eq_attr "mode" > "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF") > (eq_attr "memory" "load")))) > "znver4-direct,znver5-load,znver4-fpu") > > (define_insn_reservation "znver4_sse_mov_fp_store" 1 > (and (eq_attr "cpu" "znver4") > (and (eq_attr "type" "ssemov") > - (and (eq_attr "mode" > "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") > + (and (eq_attr "mode" > "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF") > (eq_attr "memory" "store")))) > "znver4-direct,znver4-fp-store") > > (define_insn_reservation "znver5_sse_mov_fp_store" 1 > (and (eq_attr "cpu" "znver5") > (and (eq_attr "type" "ssemov") > - (and (eq_attr "mode" > "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") > + (and (eq_attr "mode" > "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF") > (eq_attr "memory" "store")))) > "znver4-direct,znver5-fp-store256") > > -- Richard Biener <rguent...@suse.de> SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg, Germany; GF: Ivo Totev, Andrew McDonald, Werner Knoblich; (HRB 36809, AG Nuernberg)
