On 2012-07-31 11:17, Ulrich Weigand wrote: > This doesn't look correct: > + /* Emit a strict_low_part pattern if possible. */ > + if (bitpos == 0 && GET_MODE_BITSIZE (smode) == bitsize) > > With bitpos == 0 we need to insert into the *high* part, not > the low part on a big-endian platform. This probably causes > this incorrect code below: > icm %r5,3,0(%r12)
Oops, yes. I forget about bits-big-endian. > Just a plain OR is preferable to a RISBG. I guess the point of the > RISBG is that you can avoid the extra shift ... Now, if that shift > can be moved ahead of the loop, that may not be all that big of a > win. On the other hand, these loops hopefully don't loop very often > if we don't have a lot of contention ... Indeed. So it's mostly about minimizing size. I guess with RISBG available we can always implement with an input in memory with two insns -- full addressing mode on a load plus the risbg to shift and insert. If we use ICM, we might get away with 1 insn, but might need a second to reload the address into an s_operand. r~
